[15 pts]
1- Explain the meaning of each term in the list below. Be sure that you describe how each item is used within the pseudo-computer discussed in class.
Operation code (opcode)
ALU
Effective Address
Program Counter (PC)
Internal Data Bus
[15 pts]
2- Consider a CPU with 1-address format that has a memory unit with a capacity of 1K (K = 1024) words and supports 32 instructions. The instruction word is divided into three parts: opcode (Opcode) field, indirect addressing mode (I) bit, and an address (Address) field. For your information, given an address, indirect addressing is where
If I-bit = 0, the operand is located in M[address].
If I-bit = 1, the operand is located in M[M[address]].
Draw the instruction word format indicating the number of bits and the function of each field.
[24 pts]
3- For the pseudo-CPU shown in Figure 3.9 in the textbook, state whether or not each of the following microoperations can be performed in a single clock cycle. Be sure to provide an explanation for each answer. Assume PC and MAR each contain 12 bits, AC and MDR each contain 16 bits, and IR is 4 bits. You may assume that the AC register is connected as shown in the diagram below.
MAR ← AC, MDR ← MAR
IR ← MDR, MAR ← MDR
MAR ← MDR, MDR ← M(MAR)
MDR←AC+1
AC←MDR,PC←PC+1
PC←PC+AC
[24 pts]
4- Consider the following hypothetical 1-address assembly instruction called “Store Accumulator Indirect with Post-increment” of the form
STA (x)+ ; M(M(x)) ← AC, M(x) ← M(x)+1
Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP (as shown in the diagram below). An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits, and IR is 4 bits. Give the sequence of microoperations required to implement the Execute cycle (Fetch cycle is given below) for the above STA (x)+ instruction. Your solution should result in exactly 8 microoperations for the execute cycle. Assume PC is currently pointing to the STA (x)+ instruction and only PC and AC have the capability to increment/decrement themselves.
Fetch Cycle
Step 1: MAR ←PC;
Step 2:
MDR ←M(MAR), PC ← PC+1
; Read inst. & increment PC
Step 3:
IR ← MDRopcode, MAR← MDRaddress
[22 pts]
5- Based on the initial register and data memory contents shown below (represented in hexadecimal), show how these contents are modified (in hexadecimal) after executing each of the following AVR assembly instructions. Do not be concerned about what happens to the Status Register (SREG) after the operation. Instructions are
unrelated.
(i)
ldi
r27, 85
(ii)
ror
r3
(iii) adc
r2, r1
r28
(iv) sts
$0007,
(v)
sbiw
XH:XL,
2
