Lab Sheet 2 Solution

Learning Objectives:

Combinational digital circuit modeling
Constructing a larger module using a smaller module



Introduction:




In the first lab, we have learned how to simulate digital circuits using different types of modeling (i.e. Gate level, Data flow, Behavioral) in VeriLog. In this lab we will do more practice on combinational circuit simulation. Also, we will learn the hierarchical modeling (i.e. implement a larger module using a smaller module).




Problem Description:




Implement a gate level modeling of a 4x1 multiplexer. Further using the 4x1 MUX module, implement a 16x1 multiplexer.







Solution:

module mux4to1_gate(out,in,sel);




input [0:3] in;

input [0:1] sel;

output out;

wire a,b,c,d,n1,n2,a1,a2,a3,a4;




not n(n1,sel[1]);

not nn(n2,sel[0]);




and (a1,in[0],n1,n2); and (a2,in[1],n2,sel[1]);




and (a3,in[2],sel[0],n1); Sample Multiplexer Circuit and (a4,in[3],sel[0],sel[1]);




or or1(out,a1,a2,a3,a4);

endmodule




module mux16to1(out,in,sel);




input [0:15] in;

input [0:3] sel;

output out;

wire [0:3] ma;




mux4to1_gate mux1(ma[0],in[0:3],sel[2:3]); mux4to1_gate mux2(ma[1],in[4:7],sel[2:3]); mux4to1_gate mux3(ma[2],in[8:11],sel[2:3]); mux4to1_gate mux4(ma[3],in[12:15],sel[2:3]); mux4to1_gate mux5(out,ma,sel[0:1]);




endmodule

module testmux_16;




reg [0:15] in;

reg [0:3] sel;

wire out;




mux16to1 mux(out,in,sel);




initial

begin




$monitor("in=%b | sel=%b | out=%b",in,sel,out); end




initial

begin




in=16'b1000000000000000; sel=4'b0000; #3 in=16'b0100000000000000; sel=4'b0001; #3 in=16'b0010000000000000; sel=4'b0010; #3 in=16'b0001000000000000; sel=4'b0011; #3 in=16'b0000100000000000; sel=4'b0100; #3 in=16'b0000010000000000; sel=4'b0101; #3 in=16'b0000001000000000; sel=4'b0110; #3 in=16'b0000000100000000; sel=4'b0111; #3 in=16'b0000000010000000; sel=4'b1000; #3 in=16'b0000000001000000; sel=4'b1001; #3 in=16'b0000000000100000; sel=4'b1010; #3 in=16'b0000000000010000; sel=4'b1011; #3 in=16'b0000000000001000; sel=4'b1100; #3 in=16'b0000000000000100; sel=4'b1101; #3 in=16'b0000000000000010; sel=4'b1110; #3 in=16'b0000000000000001; sel=4'b1111;

end

endmodule




Exercise-1




Consider the circuit diagram for full adder using a 3x8 decoder given below.

It takes 3-bit input number and produce Sum and Carry bit as an output




Equation

S(x, y, z) = (1,2,4,7)




C(x, y, z) = (3,5,6,7)
































































Write Verilog code to implement a full adder as given in the above circuit

Write 3-to-8 decoder using Gate level model.



Name the module as DECODER( )

Write full adder using Data flow model



Name the module as FADDER( )




Write appropriate test bench module to check the correctness of your design. Specify all possible combinations in the test bench.




Circuit diagram for 3-to-8 line decoder is as follows:


















































































Solution:




module DECODER(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z);

input x,y,z;




output d0,d1,d2,d3,d4,d5,d6,d7;

wire x0,y0,z0;

not n1(x0,x);

not n2(y0,y);

not n3(z0,z);

and a0(d0,x0,y0,z0);

and a1(d1,x0,y0,z);

and a2(d2,x0,y,z0);

and a3(d3,x0,y,z);

and a4(d4,x,y0,z0);

and a5(d5,x,y0,z);

and a6(d6,x,y,z0);

and a7(d7,x,y,z);




endmodule




module FADDER(s,c,x,y,z);




input x,y,z;

wire d0,d1,d2,d3,d4,d5,d6,d7;

output s,c;




DECODER dec(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z); assign s = d1 | d2 | d4 | d7,

c = d3 | d5 | d6 | d7;




endmodule




module testbench;

reg x,y,z;

wire s,c;




FADDER fl(s,c,x,y,z);

initial




$monitor(,$time,"x=%b,y=%b,z=%b,s=%b,c=%b",x,y,z,s,c); initial

begin

#0 x=1'b0;y=1'b0;z=1'b0;

#4 x=1'b1;y=1'b0;z=1'b0;

#4 x=1'b0;y=1'b1;z=1'b0;

#4 x=1'b1;y=1'b1;z=1'b0;

#4 x=1'b0;y=1'b0;z=1'b1;

#4 x=1'b1;y=1'b0;z=1'b1;

#4 x=1'b0;y=1'b1;z=1'b1;

#4 x=1'b1;y=1'b1;z=1'b1;




end

endmodule




Task to do:

Implement a 8-bit adder circuit using the above 1-bit adder module.
Implement a 32-bit adder using 8-bit adder module.
Exercise-2




Consider the given circuit diagram which performs add and subtract operations. The Input M controls the operation (M=1 for subtract and M=0 for the add operation). Output V=1, if overflow occurs otherwise V=0.




Tasks to be done:

Implement a FULLADDER() module using behavioral modeling.



Use FULLADDER() to implement ADDSUB() module which takes two 4-bit numbers and one control input M as input argument and produces an 4-bit sum/sub with an overflow bit V.