$24
VHDL Assignment #3: Design and Simulation of Adder Circuits Solution
2 Learning Outcomes
After completing this lab you should know how to:
• Use VHDL statements to implement different adder circuits
• Write efficient VHDL codes
• Perform functional simulation
• Perform basic timing analysis
You will also have a better understanding of the concept of synthesis of logic circuits.
3 VHDL Description of Adder Circuits
In this assignment, you will be asked to perform the design and simulation of the following two adder circuits: (a) a 4-bit ripple-carry adder; and (b) a one-digit binary coded decimal (BCD) adder. Details of the assignments are described below.
3.1 Ripple-Carry Adder (RCA)
In this section, you will implement a structural description of a 4-bit ripple-carry adder using basic addition components: half-adders and full-adders.
3.1.1 Structural Description of a Half-Adder in VHDL
A half-adder is a circuit that takes two binary digits as inputs, and produces the result of the addition of the two bits in the form of a sum and carry signals. The carry signal represents an overflow into the next digit of a multi-digit addition. Using the following entity definition for your VHDL code, implement a structural description of the half-adder.
l i b r a r y IEEE;
u s e IEEE.STD_LOGIC_1164.ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y h a l f _ a d d e r i s
p o r t ( a : i n s t d _ l o g i c ;
McGill University ECSE 222 – Digital Logic (Fall 2020)
VHDL Assignment #3
2
b : i n s t d _ l o g i c ;
s :
o u t
s t d _ l o g i c ;
c :
o u t
s t d _ l o g i c ) ;
end h a l f _ a d d e r ;
After you have described your structural style of the half-adder in VHDL, you are required to test your circuit.
Write a testbench code and perform an exhaustive test of your VHDL description of the half-adder.
3.1.2 Structural Description of a Full-Adder in VHDL
Unlike the half-adder, a full-adder adds binary digits while accounting for values carried in (from a previous stage addition). Write a structural VHDL description for the full-adder circuit using the half-adder circuit that you designed in the previous section. Use the following entity declaration for your structural VHDL description of the full-adder.
l i b r a r y IEEE;
u s e IEEE.STD_LOGIC_1164.ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y f u l l _ a d d e r i s
p o r t ( a : i n s t d _ l o g i c ;
b : i n s t d _ l o g i c ;
c_in : i n s t d _ l o g i c ;
s : o u t s t d _ l o g i c ;
c_out : o u t s t d _ l o g i c ) ;
end f u l l _ a d d e r ;
After you have described your circuit in VHDL, write a testbench code and perform an exhaustive test of your VHDL description of the full-adder.
3.1.3 Structural Description of a 4-bit Ripple-Carry Adder (RCA) in VHDL
Using the half-adder and full-adder circuits implemented in the two previous sections, implement a 4-bit carry-ripple adder. Write a structural VHDL code for the 4-bit RCA using the following entity declaration.
l i b r a r y IEEE;
u s e IEEE.STD_LOGIC_1164.ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y r c a _ s t r u c t u r a l i s
p o r t
( A :
i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
B :
i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
S : o u t
s t d _ l o g i c _ v e c t o r
(4
downto
0));
end
r c a _ s t r u c t u r a l ;
Note that S(4) contains the carry-out of the 4-bit adder. After you have described your circuit in VHDL, write a testbench code and perform an exhaustive test of your VHDL structural description of the 4-bit RCA.
3.1.4 Behavioral Description of a 4-bit RCA in VHDL
In this part, you are required to implement the 4-bit RCA using behavioral description. One way to obtain a behavioral description is to use arithmetic operators in VHDL (i.e., “+”). Write a behavioral VHDL code for the 4-bit RCA using the following entity declaration for your behavioral VHDL description.
l i b r a r y IEEE;
u s e IEEE.STD_LOGIC_1164.ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y r c a _ b e h a v i o r a l i s
p o r t
( A :
i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
B :
i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
S : o u t
s t d _ l o g i c _ v e c t o r
(4
downto
0));
end
r c a _ b e h a v i o r a l ;
McGill University ECSE 222 – Digital Logic (Fall 2020)
VHDL Assignment #3
3
After you have described your circuit in VHDL, write a testbench code and perform an exhaustive test of your VHDL behavioral description of the 4-bit RCA.
3.2 VHDL Description of a One-Digit BCD Adder
In this section, you will implement a one-digit BCD adder in VHDL. A one-digit BCD adder adds two four-bit numbers represented in a BCD format. The result of the addition is a BCD-format 4-bit output, representing the decimal sum, and a carry that is generated if this sum exceeds a decimal value of 9 (see slides of Lecture #11).
3.2.1 Structural Description of a BCD Adder in VHDL
In this part, you are required to implement the BCD adder using structural description. You are allowed to use either behavioral or structural style of coding for your implementation. Using the following entity definition. Use the following entity declaration.
l i b r a r y IEEE;
u s e IEEE. S T D _ L O G I C _ 1 1 1 6 4 .ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y b c d _ a d d e r _ s t r u c t u r a l i s
p o r t
( A :
i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
B :
i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
S : o u t
s t d _ l o g i c _ v e c t o r
(3
downto
0)
;
end
C : o u t s t d _ l o g i c ) ;
b c d _ a d d e r _ s t r u c t u r a l ;
After you have implemented the one-digit BCD adder in VHDL, you are required to test your circuit. Write a testbench code and perform an exhaustive test of your VHDL structural description of the one-digit BCD adder.
3.2.2 Behavioral Description of a BCD Adder in VHDL
In this part, you are required to implement the BCD adder using behavioral description. You are encouraged to base your code on the VHDL code in Section 5.7.3 of the textbook, so that you learn about conditional signal assignments (these are explained in detail in the same section as well as in the Appendix in Section A.7.4). Use the following entity declaration.
l i b r a r y IEEE;
u s e IEEE. S T D _ L O G I C _ 1 1 1 6 4 .ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y b c d _ a d d e r _ b e h a v i o r a l i s
p o r t (
A : i n s t d _ l o g i c _ v e c t o r (3
downto 0) ;
B : i n
s t d _ l o g i c _ v e c t o r
(3
downto
0) ;
S : o u t
s t d _ l o g i c _ v e c t o r
(3
downto
0)
;
C : o u t s t d _ l o g i c ) ;
end b c d _ a d d e r _ b e h a v i o r a l ;
After you have implemented the one-digit BCD adder in VHDL, you are required to test your circuit. Write a testbench code and perform an exhaustive test for your VHDL behavioral description of the one-digit BCD adder.
3.3 Timing Analysis and Critical Path
In this part you will learn how to perform timing analysis in the EDAPlayground platform. You will also be able to find the critical path of a given circuit.
The critical path is the longest path in the circuit which defines the speed of the circuit. The speed of a digital circuit is measured in terms of latency and throughput. Latency is the time needed for the circuit to produce an output for a given input (i.e., the total propagation delay (time) from the input to the output), and it is expressed in units of time. Alternatively, throughput refers to the rate at which data can be processed. In this assignment, we only consider the latency as a metric to measure the speed of the circuit.
In general, digital circuits are subject to timing constraints dictated by the target application. Whether a circuit meets these timing constraints can only be known after the circuit is synthesized. After synthesis is performed, the designer can analyze the circuit to determine whether timing constraints were satisfied using the term slack.
McGill University ECSE 222 – Digital Logic (Fall 2020)
VHDL Assignment #3
4
Slack is the margin by which a timing requirement is met or not met; it is the difference between the required arrival time and the actual arrival time. A positive slack value indicates the margin by which a requirement was met. A negative slack value indicates the margin by which a requirement was not met.
To simulate timing constraints, we can add time constraint files to our design. Here, we will use the 4-bit RCA that we designed in Section 3.1.3 (structural description) as an example. Please note that for your assignment submission, you will be required to analyze the timing of the BCD adder, NOT the RCA that is used here as an example only.
Create a new file by clicking on the (+) icon (next to testbench.vhd).
Name the file rca.sdc. Note that sdc stands for Synopsis Design Constraints.
The maximum delay can be specified in the sdc file using the following command:
s e t _ m a x _ d e l a y - from [ g et _p or t s < n a m e _ o f _ i n p u t _ p o r t > ] - t o [ ge t_ p or ts < n a m e _ o f _ o u t p u t _ p o r t > ] <time i n nano seconds>
In this example, we set the delay to be 20 nsec (nano seconds) from the input A to the output S (for all possible paths), and 15 nsec from the input B to the output S (for all possible paths).
s e t _ m a x _ d e l a y
- from
[ g et _p or t s
A [*]]
- t o
[ ge t_ p or ts
S [*]]
20
s e t _ m a x _ d e l a y
- from
[ g et _p or t s
B [*]]
- t o
[ ge t_ p or ts
S [*]]
15
Update your run.do file to include time delay related information. The updated run.do file should look like this:
a d d _ i n p u t _ f i l e rca . sdc
s e t u p _ d e s i g n - m a n u f a c t u r e r Xilinx - family Artix -7 - part 7 A 1 0 0 T C S G 3 2 4 foreach arg $ :: argv {
a d d _ i n p u t _ f i l e $arg
}
compile
s y n t h e s i z e
a u t o _ w r i t e pr ec is i on . v
r e p o r t _ o u t p u t _ f i l e _ l i s t
r e p o r t _ a r e a
r e p o r t _ t i m i n g
exec cat p re ci s io n . v
McGill University ECSE 222 – Digital Logic (Fall 2020)
VHDL Assignment #3
5
Make sure that your system settings look like this:
Click run (remember to set the simulator to Mentor Precision 2019.2 for this part), and you will be able to see the timing analysis information in the compiler log. In this example, the log looks like this:
For example, the critical path from input A(3) to output S(4) exhibits a positive slack of 15.019 ns, which means that the circuit meets the requirement.
McGill University ECSE 222 – Digital Logic (Fall 2020)
VHDL Assignment #3
6
4 Deliverables
Once completed, you are required to submit a report explaining your work in detail, including answers to the questions related to this lab. You will find the questions in the next section. You must also submit all of your VHDL, run.do, and .sdc files along with Log content of the synthesized circuits and timing analysis. You must also submit all of your testbench files. If you fail to submit any part of the required deliverables, you will incur grade penalties as described in the syllabus.
5 Questions
Please note that even if some of the waveforms may look the same, you still need to include them separately in the report.
1. Briefly explain your VHDL code implementation of all circuits.
2. Show representative simulation plots of the half-adder circuit for all possible input values.
3. Show representative simulation plots of the full-adder circuit for all possible input values.
4. Show representative simulation plots of both behavioral and structural descriptions of the 4-bit RCA for all possible input values.
5. Show representative simulation plots of both behavioral and structural descriptions of the one-digit BCD adder circuit for all possible input values.
6. Perform timing analysis of the one-digit BCD adder and find the critical path(s) of the circuit. What is the delay of the critical path(s)? Assuming that an additional delay of 10 ns can be added to the critical path(s) due to wiring, what should be the setmaxdelay command to ensure a positive slack of 5 ns for the circuit (write the complete setmaxdelay command).
7. Report the number of pins and logic modules used to fit your BCD adder designs on the FPGA board.
RCA
One-digit BCD adder
Structural Behavioral
Structural Behavioral
Logic Utilization (in LUTs)
Total pins
McGill University ECSE 222 – Digital Logic (Fall 2020)
