Objective
Implement the timer and stopwatch functions of the electronic clock.
Prerequisite
Fundamentals of logic gates.
Logic modeling in Verilog HDL.
Simple logic development and FSM control
Experiments
Implement a stopwatch function with the FPGA board.
1.1 Use the four (Seven-Segment Displays, SSDs) as the display. The left two digits represent the minute and the right two digits represent the second.
1.2 Use two push buttons to control the function. Use one button to control start/stop and the other to control the lap and reset. When the stopwatch counts, press the ‘lap’ button will freeze the SSDs but the stopwatch continues counting, and when press the ‘lap’ button again, the SSDs will start to show current time.
Implement a timer (can support as long as 23:59) with the following functions.
2.1 Use one DIP switch as the ‘setting’ control. When the ‘setting’ is ON, you can use two buttons to set the hour and minute.
2.2 Use other two buttons to control the timer operation. One button for start/stop and the other button for pause/resume.
2.3 When the time goes to 0, light up all the LEDs.
(Bonus) Integrate the above two functions together with only three buttons.
Note: You can use one addition button for reset in this lab.
TA:
© Ma, Hsi-Pin, Lab for Reliable Computing (LaRC), EE, NTHU. Spring, 2018
