Programming Assignment 2 Part 2 Solution

For this part of the assignment, you should complete the remaining ALU functions - SUB, SLT, SRL,




SLL, and SRA - and make sure that your ALU has properly functioning zero, equal, and overflow bits.




Also make sure that you create testbenches to test functionality!




Extra Credit: If you implement a carry-lookahead adder for part 2, you will receive up to 10 extra credit points. However, we strongly suggest that you stick with a simpler adder type for part 1!




Submit the following on Canvas for each part:




Your Xilinx project



Sketches of each of the main component circuits (SLT, SLL, SRL, ADD, SUB, SRA). Make sure any scans are legible and/or any pictures are clear.



A description (one or two paragraphs) of your simulation/testing methodology



Unzipping the compressed file should yield the following general directory structure (the individual file/folder names don’t have to match what is written below, but be descriptive when appropriate):




lab2_xilinx_project/ sketches/ description.doc / description.txt / description.pdf




As you work on this assignment, remember that you should only have one module for each source file. This helps keep your code much more organized and modular. Instructions for adding new modules and testbenches can be found here. Also, please be sure to thoroughly comment your Verilog!




Here is the rubric we will be using for grading:







Component
Part 1 Points
Part 2 Points






Circuit Sketches
5
15
Simulation Description
2
6
16:1 mux
4


Student testbench rigor (see below)
5
15
ALU’s functional correctness under instructor testbench


40
Synthesis (works or not)
4
4
Extra Credit


10












Student testbench rigor




A portion of the grade will depend on the testbench you write to ensure that your Verilog code is correct. Please test at least one standard case and one special case for each op code (you should also consider testing many more cases otherwise your implementation may fail on our testbench). A special case is one where one of the flags is set (overflow, equal, or zero). You may want to create new tests







4
Programming Assignment 2: ALU CS141










for each new gate that you create (for example a test_adder.v, test_sll.v, etc..)







Submission




You should submit the assignment to the page on Canvas. Please see the submission guidelines for how to prepare your project for submission.




Generate tutorial




If you are copying many lines that have a similar form, you may find it useful to use the generate statement, which specifies the generation of hardware objects. A simplified syntax for the generate statement is;




generate




genvar [index_variables];




for ([initial_assignment]; [expression]; [step_assignment])




begin [: optional_label]




[concurrent_constructs];




...;




end




endgenerate




Here is an example to create a cascading xor circuit (which you saw in the last programming assignment can determine the odd parity of an input signal). Here is the schematic:








































Figure from FPGA Prototyping by SystemVerilog Examples By Pong P. Chu.




Verilog has shorthand to do this with one operator but we will build the circuit from scratch for demonstration purposes.




module cascade_xor(a, y);




input wire [7:0] a;




output wire y;




wire [7:0] p;




assign p[0] = a[0];




generate




genvar i;




for (i = 1; i < 8; i = i + 1) begin










5
Programming Assignment 2: ALU CS141










xor xor_gen (p[i], a[i], p[i-1]);




end




endgenerate




assign y = p[7];




endmodule












































































































































































Modified by Zach Yedidia on February 9, 2019 6