Project 04 Solution

IMPORTANT!




Please follow the submission guidelines below or your submission will be rejected.




You are expected to submit both a lab report and the source files to Blackboard in a single submission attempt.



The source codes must be under a single project.



The VHDL project needs to be exported from Xilinx ISE Design Suite. To export VHDL project file, please refer to Blackboard - Content - Lab - Exporting VHDL Project Files.



Naming convention:
Report: “FirstName_LastName_Project_XX_MMY.pdf”




Project: “FirstName_LastName_Project_XX_MMY.zip”




Replace “XX” and “Y” with the actual project number and section number, respectively.










In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) 14.7 to complete the following tasks.




Please read the instructions carefully. Failing to follow the instructions would lead to significant point deductions.




Task 1: Positive Edge Triggered D Flip-Flop (7 points)




Write a VHDL program to implement a Positive Edge Triggered D Flip-Flop.

Please adopt the following entity declaration.














































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In this task, use the LD component (essentially a D Latch) defined in the UNISIM library. In order to use the LD component, please make sure you have the following lines in your VHDL program to include the UNISIM library.



















Then you will need to declare the component in the VDHL architecture definition.

For example:





































Then you can use it like this:
















In your program, please make sure you name the input/output signals according to the truth table.


































Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.














































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Requirement(s):

In your VHDL implementation




Please follow the structural design method;
Make use of the LD component.



Deliverable(s):









































































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Your report:




Use your own language to describe the function of the module to be implemented in VHDL. (1 point)



Draw a circuit diagram of the module to show the design. (1 point)



Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (2 points)



Your project file(s):

Can compile without any errors. (1 point)
Can run simulations without any errors. (1 point)



Note: no points will be given if requirements are not satisfied.



















Task 2: T Flip-Flop (7 points)




A T (toggle) flip-flop changes state on every tick of the clock. The figures below show the symbol and illustrate the behavior of a positive-edge-triggered T flip-flop. Note that according to the logic symbol, the T flip-flop is edge triggered.































T flip-flop can be built from a positive-edge-triggered (PET) D flip-flop. In the previous task, you implemented such a PET D flip-flop. In this task, please write a VHDL program to implement a T flip-flop by using the PET D flip-flop. Please adopt the following entity declaration.






























Use the following test-bench program to run simulations and to validate your design.










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Requirement(s):

In your VHDL implementation

Please follow the structural design method;
Make use of the module(s) you implemented before.



Deliverable(s):







Your report:

Draw a circuit diagram of the module to show the design. (1 point)
Use your own language to explain how the circuit works. (1 point)



Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (2 points)



Your project file(s):

Can compile without any errors. (1 point)
Can run simulations without any errors. (1 point)



Note: no points will be given if requirements are not satisfied.




























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Task 3: 4-bit Binary Ripple Counter (6 points)







An n-bit binary counter can be constructed using n T flip-flops. In this task, please use the given design to implement a 4-bit binary ripple counter in VHDL.




Please use the following entity declaration for the counter.





































Use the following test-bench program to run simulations and to validate your design.

































































































Requirement(s):




In your VHDL implementation

Please follow the structural design method;
Make use of the module(s) you implemented before.






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Deliverable(s):







Your report:

Use your own language to explain how the circuit works. (1 point)



Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (2 points)



Your project file(s):

Can compile without any errors. (1 point)
Can run simulations without any errors. (1 point)



Note: no points will be given if requirements are not satisfied.































































































































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