$29
Systems and Networks Project 2 Solution
We have spent the last few weeks implementing our 32-bit datapath. The simple 32-bit LC-898 is capable of performing advanced computational tasks and logical decision making. Now it is time for us to move on to something more advanced|the upgraded LC-898a enables the ability for programs to be interrupted. Your assignment is to fully implement and test interrupts using the provided datapath and CircuitSim. You will hook up the interrupt and data lines to the new timer device, modify the datapath and microcontroller to support interrupt operations, and write an interrupt handler to operate this new device.
• Requirements
Before you begin, please ensure you have done the following:
• Download the proper version of CircuitSim. A copy of CircuitSim is available under Files on Canvas. You may also download it from the CircuitSim website (https://ra4king.github.io/CircuitSim/). In order to run CircuitSim, Java must be installed. If you are a Mac user, you may need to right-click on the JAR le and select \Open" in the menu to bypass Gatekeeper restrictions.
• CircuitSim is still under development and may have unknown bugs. Please back up your work using some form of version control, such as a local/private git repository or Dropbox. Do not use public git repositories; it is against the Georgia Tech Honor Code.
• The LC-898a assembler is written in Python. If you do not have Python 3.7 or newer installed on your system, you will need to install it before you continue.
• What We Have Provided
◦ A reference guide to the LC-898a is located in Appendix A: LC-898a Instruction Set Architecture. Please read this rst before you move on! The reference introduces several new instructions that you will implement for this project.
◦ A CircuitSim circuit (int-devices.sim) containing a timer device and garden thermometer device subcircuit that you will use for this project. You should copy and paste the contents of the new devices into subcircuits in your main circuit le.
◦ A new microcode con guration spreadsheet microcode.xlsx with additional bits for the new signals that will be added in this project.
◦ A timer device that will generate an interupt signal at regular intervals. The pinout and functionality of this device are described in Adding an External Timer Device.
◦ A garden thermometer device that will generate an interrupt signal at regular intervals, and provides garden temperature readings. The pinout and functionality of this device are described in Adding a Garden Thermometer.
◦ An incomplete assembly program prj2.s that you will complete and use to test your interrupt capa-bilities.
◦ An assembler with support for the new instructions to assemble the test program.
◦ An incomplete LC-898a datapath circuit (LC-898a.sim) that you may add the basic interrupt support onto will be provided Tuesday, February 11, after the one-time forgiveness period for Project 1 has passed. You are also free to build o of your own Project 1 datapath, but you must rename the le to LC-898a.sim. Most of the work can be easily carried over from one datapath to another.
Project 2 CS 2200 - Systems and Networks Spring 2020
• We will also release a microcode.xlsx microcode le that meets the requirements of Project 1, but feel free to supply your own.
• Phase 1 - Implementing a Basic Interrupt
Datapath
DrData
DATA
Microcontroller
INT
INTA
Timer Device
INTA
Other Devices
Figure 1: Basic Interrupt Hardware for the LC-898a Processor
For this assignment, you will add interrupt support to the LC-898a datapath. Then, you will test your new capabilities to handle interrupts using an external timer device.
Work in the LC-898a.sim le. If you wish to use your existing datapath, make a copy with this name, and add the devices we provided.
4.1 Interrupt Hardware Support
First, you will need to add the hardware support for interrupts.
You must do the following:
1. Our processor needs a way to turn interrupts on and o . Create a new one-bit \Interrupt Enable" (IE) register. You’ll connect this register to your microcontroller in a later step.
Project 2 CS 2200 - Systems and Networks Spring 2020
2. Create the INT line. The external device you will create in 4.2 will pull this line high (assert a ’1’) when they wish to interrupt the processor. Because multiple devices can share a single INT line, only one device can write to it at once. When a device does not have an interrupt, it neither pulls the line high nor low. You must accomodate this in your hardware by making sure that the nal value going to the microcontroller always has a value (i.e. not a blue wire in CircuitSim).
3. When a device receives an IntAck signal, it will drive a 32-bit device ID onto the I/O Data Bus. To prevent devices from interfering with the processor, the I/O Data Bus is attached to the Main Bus with a tri-state driver. Create this driver and the bus, and attach the microcontroller’s DrDATA signal to the driver.
4. Modify the datapath so that the PC starts at 0x08 when the processor is reset. Normally the PC starts at 0x00, however we need to make space for the interrupt vector table (IVT). Therefore, when you actually load in the test code that you will write, it needs to start at 0x08. Please make sure that your solution ensures that datapath can never execute from below 0x08 - or in other words, force the PC to drive the value 0x08 if the PC is pointing in the range of the vector table.
5. Create hardware to support selecting the register $k0 within the microcode. This is needed by some interrupt related instructions. Because we need to access $k0 outside of regular instructions, we cannot use the Rx / Ry / Rz bits. HINT: Use only the register selection bits that the main ROM already outputs to select $k0.
4.2 Adding an External Timer Device
Hardware timers are an essential device in any CPU design. They allow the CPU to monitor the passing of various time intervals, without dedicating CPU instructions to the cause.
The ability of timers to raise interrupts also enables preemptive multitasking, where the operating system periodically interrupts a running process to let another process take a turn. Timers are also essential to ensuring a single misbehaving program cannot freeze up your entire computer.
You will connect an external timer device to the datapath. It is internally con gured to have a device ID of 0x0 and a 2000-cycle tick timer interval.
The pinout of the timer device is described below. If you like, you may also examine the internals of the device in CircuitSim.
• CLK: The clock input to the device. Make sure you connect this to the same clock as the rest of your circuit.
• INT: The device will begin to assert this line when its time interval has elapsed. It will not be lowered until the cycle after it receives an INTA signal.
• INTA IN: When the INTA IN line is asserted while the device has asserted the INT line, it will drive its device ID to the DATA line and lower its INT line on the next clock cycle.
• INTA OUT: When the INTA IN line is asserted while the device does not have an interrupt pending, its value will be propagated to INTA OUT. This allows for daisy chaining of devices.
• DATA: The device will drive its ID (0x0) to this line after receiving an INTA.
The INT and DATA lines from the timer should be connected to the appropriate buses that you added in the previous section.
4.3 Microcontroller Interrupt Support
Before beginning this part, be sure you have read through Appendix A: LC-898a Instruction
Set Architecture and Appendix B: Microcontrol Unit and pay special attention to the new
Project 2 CS 2200 - Systems and Networks Spring 2020
instructions. However, for this part of the project, you do not need to worry about the LdDAR signal or the IN instruction.
In this part of the assignment you will modify the microcontroller and the microcode of the LC-898a to support interrupts. You will need to do the following:
1. Be sure to read the appendix on the microcontroller before starting this section.
2. Modify the microcontroller to support asserting four new signals:
(a) LdEnInt & EnInt to control whether interrupts are enabled/disabled. You will use these 2 signals to control the value of your interrupts enabled register.
(b) IntAck to send an interrupt acknowledge to the device.
(c) DrDATA to drive the value on the I/O Data Bus to the Main Bus.
3. Extend the size of the ROM accordingly.
4. Add the fourth ROM described in Appendix B: Microcontrol Unit to handle onInt.
5. Modify the FETCH macrostate microcode so that we actively check for interrupts. Normally this is done within the INT macrostate (as described in Chapter 4 of the book and in the lectures) but we are rolling this functionality in the FETCH macrostate for the sake of simplicity. You can accomplish this by doing the following:
(a) First check to see if the CPU should be interrupted. To be interrupted, two conditions must be true: (1) interrupts are enabled (i.e., the IE register must hold a ’1’), and (2), a device must be asserting an interrupt.
(b) If not, continue with FETCH normally.
(c) If the CPU should be interrupted, then perform the following:
i. Save the current PC to the register $k0.
ii. Disable interrupts.
iii. Assert the interrupt acknowledge signal (IntAck). Next, drive the device ID from the I/O Data Bus and use it to index into the interrupt vector table to retrieve the new PC value. The device will drive its device ID onto the I/O Data Bus one clock cycle after it receives the IntAck signal.
iv. This new PC value should then be loaded into the PC.
Note: onInt works in the same manner that CmpOut did in Project 1. The processor should branch to the appropriate microstate depending on the value of onInt. onInt should be true when interrupts are enabled AND when there is an interrupt to be acknowledged. Note: The mode bit mechanism discussed in the textbook has been omitted for simplicity.
6. Implement the microcode for three new instructions for supporting interrupts as described in Chapter
4. These are the EI, DI, and RETI instructions. You need to write the microcode in the main ROM controlling the datapath for these three new instructions. Keep in mind that:
(a) EI sets the IE register to 1.
(b) DI sets the IE register to 0.
(c) RETI loads $k0 into the PC, and enables interrupts.
Project 2 CS 2200 - Systems and Networks Spring 2020
4.4 Implementing the Timer Interrupt Handler
Our datapath and microcontroller now fully support interrupts from devices, BUT we must now implement the interrupt handler t1_handler within the prj2.s le to support interrupts from the timer device while also not interfering with the correct operation of any user programs.
In prj2.s, we provide you with a program that runs in the background. For this part of the project, you need to write interrupt handler for the timer device (device ID 0x0). You should refer to Chapter 4 of the textbook to see how to write a correct interrupt handler. As detailed in that chapter, your handler will need to do the following:
1. First save the current value of $k0 (the return address to where you came from to the current handler)
2. Enable interrupts (which should have been disabled implicitly by the processor within the INT macrostate).
3. Save the state of the interrupted program.
4. Implement the actual work to be done in the handler. In the case of this project, we want you to increment a counter variable in memory, which we have already provided.
5. Restore the state of the original program and return using RETI.
The handler you have written for the timer device should run every time the device’s interrupt is triggered. Make sure to write the handler such that interrupts can be nested. With that in mind, interrupts should be enabled for as long as possible within the handlers.
You will need to do the following:
1. Write the interrupt handler (should follow the above instructions or simply refer to Chapter 4 in your book). In the case of this project, we want the interrupt handler to keep time in memory at the predetermined location: 0xFFFF
2. Load the starting address of the rst handler you just implemented in prj2.s into the interrupt vector table at the appropriate addresses (the table is indexed using the device ID of the interrupting device).
Test your design before moving onto the next section. If it works correctly, you should see a location in memory increment as the program runs.
Project 2 CS 2200 - Systems and Networks Spring 2020
• Phase 2 - Implementing Interrupts from Input Devices
Datapath
Datapath
DAR
LdDAR
DrData
ADDR
DATA
Microcontroller
INT
INTA
Garden
INTA
Timer Device
Thermometer
Other Devices
Device
Figure 2: Interrupt Hardware for the LC-898a with Basic I/O Support
Eager to put your newfound knowledge of device interrupts from CS2200 to good use, you decide to apply what you’ve learned to your second favorite hobby (besides CS2200): gardening.
You’ve rigged up a device that is able to report the temperature to an LC-898a processor via an interrupt. There’s only one issue: as of right now, your datapath can detect when an external device is ready to interrupt the processor, but it cannot retrieve data from external devices.
In this phase of the project, you will add functionality for device-addressed input. You will then make use of this functionality by adding a device simulating a garden thermometer device and writing a simple handler for the device.
5.1 Basic I/O Support
Before adding the garden thermometer device, you will rst need to add support for device addressed I/O. In order to get input from a device such as a thermometer, you will write a value to an Address Bus, which instructs the device with that address (which in this case is the same as the device ID) to write its output data to the I/O Data Bus.
You must do the following:
1. Create the device address register (DAR) and connect its enable to the LdDAR signal from your microcontroller. This register gets its input from the Main Bus, and its output will be directly connected to the Address Bus. It will allow us to send assert a value on the Address Bus while using the Main Bus for other operations.
Project 2 CS 2200 - Systems and Networks Spring 2020
2. Modify the microcontroller to support a new control signal, LdDAR. This signal will be used in order to enable writing to the DAR.
3. Implement the IN instruction in your microcode. This instruction takes a device address from the immediate, loads it into the DAR, and writes the value on the data bus into a register. When it is done, it must clear the DAR to zero (since interrupts use the data bus to communicate device IDs). Examine the format of the IN instruction and consider what signals you might raise in order to write a constant zero into the DAR.
5.2 Adding a Garden Thermometer
You will connect a garden thermometer device to your datapath that simulates a real thermometer that captures temperature readings. Its internals are similar to the timer device, meaning it asserts interrupts and handles acknowledgements in the same way. Every 2500 cycles, it will assert an interrupt signaling that a temperature has been captured. This temperature reading can be fetched as a 32-bit word by writing the device’s address to the ADDR line.
The garden thermometer device is internally con gured to have a device ID of 0x1.
Place the garden thermometer device in your datapath circuit. This device will share the INT and DATA lines with the timer you added previously. However, it should receive its INTA signal from the INTA OUT pin on the timer device. This ensures that if both the timer and garden thermometer device raise an interrupt at the same time, the timer will be acknowledged rst, and the garden thermometer device will be acknowledged after. This is known as \daisy chaining" devices.
5.3 Implementing the Garden Thermometer Interrupt Handler
Now that your LC-898a datapath can accept data from your garden thermometer device, we need to decide what to do with the data. The plants in your garden are sensitive to high temperatures. You decide you’ll monitor the rolling maximum temperature of your garden as temperature readings come in. You’ll have to implement this logic in your handler. The handler for your garden thermometer device will work similarly to the one you wrote for the timer device. However, instead of incrementing a timer at a memory location, you will be keeping track of the max temperature reading in a memory location.
In addition to the usual overhead of an interrupt handler, your thermometer handler must do the following:
1. Use the IN instruction to obtain the most recently captured temperature from the thermometer.
2. Write the value obtained from the thermometer to the memory location pointed to by the pointer which points to 0xFFE0 only if it is larger than the current max.
Make sure that you properly install the location of the new handler into the IVT.
The thermometer hardware is designed to emit a sequence of numbers representing temperature readings. If your design is working properly, you should see the value stored in the memory location increase occasionally as it updates when a new max is introduced.
To validate you’re updating the maximum temperature correctly, you can check the values that the garden thermometer device will emit by inspecting the internals of the circuit and checking the values in the ROM labeled ’Temperature Bu er’.
• Deliverables
Please submit all of the following les in a .tar.gz archive generated by one of the following:
Project 2 CS 2200 - Systems and Networks Spring 2020
• On Linux: Use the provided Make le. The Make le will work on any Unix or Linux-based machine (on Ubuntu, you may need to sudo apt-get install build-essential if you have never installed the build tools). Run make submit to automatically package your project into the correct archive format.
• On Windows: Use the provided submit.bat script. Submitting through this method will require 7zip (https://www.7-zip.org/) to be installed on your system. Run submit.bat to automatically package your project into the correct archive format.
• On Mac: Use the provided Make le. If you haven’t yet installed Command Line Tools, you’ll need to do so. If you have Xcode installed on your machine, you already have Command Line Tools. Otherwise, you can install them by either installing Xcode or installing Command Line Tools standalone from Apple’s developer site. Run make submit to automatically package your project into the correct archive format.
The generated archive should contain at a minimum the following les:
• CircuitSim datapath le (LC-898a.sim)
• Microcode le (microcode.xlsx)
• Assembly code (prj2.s)
Always re-download your assignment from Canvas after submitting to ensure that all necessary les were properly uploaded. If what we download does not work, you will get a 0 regardless of what is on your machine.
This project will be demoed. In order to receive full credit, you must sign up for a demo slot and complete the demo. We will announce when demo times are released.
Project 2 CS 2200 - Systems and Networks Spring 2020
• Appendix A: LC-898a Instruction Set Architecture
The LC-898a is a simple, yet capable computer architecture. The LC-898a combines attributes of both ARM and the LC-2200 ISA de ned in the Ramachandran & Leahy textbook for CS 2200.
The LC-898a is a word-addressable, 32-bit computer. All addresses refer to words, i.e. the rst word (four bytes) in memory occupies address 0x0, the second word, 0x1, etc.
All memory addresses are truncated to 16 bits on access, discarding the 16 most signi cant bits if the address was stored in a 32-bit register. This provides roughly 64 KB of addressable memory.
7.1 Registers
The LC-898a has 16 general-purpose registers. While there are no hardware-enforced restraints on the uses of these registers, your code is expected to follow the conventions outlined below.
Table 1: Registers and their Uses
Register Number
Name
Use
Callee Save?
0
$zero
Always Zero
NA
1
$at
Assembler/Target Address
NA
2
$v0
Return Value
No
3
$a0
Argument 1
No
4
$a1
Argument 2
No
5
$a2
Argument 3
No
6
$t0
Temporary Variable
No
7
$t1
Temporary Variable
No
8
$t2
Temporary Variable
No
9
$s0
Saved Register
Yes
10
$s1
Saved Register
Yes
11
$s2
Saved Register
Yes
12
$k0
Reserved for OS and Traps
NA
13
$sp
Stack Pointer
No
14
$fp
Frame Pointer
Yes
15
$ra
Return Address
No
1. Register 0 is always read as zero. Any values written to it are discarded. Note: for the purposes of this project, you must implement the zero register. Regardless of what is written to this register, it should always output zero.
2. Register 1 is used to hold the target address of a jump. It may also be used by pseudo-instructions generated by the assembler.
3. Register 2 is where you should store any returned value from a subroutine call.
4. Registers 3 - 5 are used to store function/subroutine arguments. Note: registers 2 through 8 should be placed on the stack if the caller wants to retain those values. These registers are fair game for the callee (subroutine) to trash.
5. Registers 6 - 8 are designated for temporary variables. The caller must save these registers if they want these values to be retained.
6. Registers 9 - 11 are saved registers. The caller may assume that these registers are never tampered with by the subroutine. If the subroutine needs these registers, then it should place them on the stack and restore them before they jump back to the caller.
Project 2 CS 2200 - Systems and Networks Spring 2020
7. Register 12 is reserved for handling interrupts. While it should be implemented, it otherwise will not have any special use on this assignment.
8. Register 13 is your anchor on the stack. It keeps track of the top of the activation record for a subroutine.
9. Register 14 is used to point to the rst address on the activation record for the currently executing process.
10. Register 15 is used to store the address a subroutine should return to when it is nished executing.
7.2 Instruction Overview
The LC-898a supports a variety of instruction forms, only a few of which we will use for this project. The instructions we will implement in this project are summarized below.
Table 2: LC-898a Instruction Set
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
ADD
0000
DR
SR1
unused
SR2
NAND
0001
DR
SR1
unused
SR2
ADDI
0010
DR
SR1
immval20
LW
0011
DR
BaseR
o set20
SW
0100
SR
BaseR
o set20
BEQ
0101
SR1
SR2
o set20
JALR
0110
RA
AT
unused
HALT
0111
unused
BGT
1000
SR1
SR2
o set20
LEA
1001
DR
unused
PCo set20
EI
1010
unused
DI
1011
unused
RETI
1100
unused
IN
1101
DR
0000
addr20
7.2.1 Conditional Branching
Conditional branching in the LC-898a ISA is provided via two instructions: the BGT ("branch if greater than") and BEQ ("branch if equal") instructions. The BEQ will branch to address "incrementedPC + o set20" only if SR1 and SR2 are equal. However, BGT will branch to address "incrementedPC + o set20" only if SR1 is greater than SR2.
Project 2 CS 2200 - Systems and Networks Spring 2020
7.3 Detailed Instruction Reference
7.3.1 ADD
Assembler Syntax
ADD DR, SR1, SR2
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
0000
DR
SR1
unused
Operation
DR = SR1 + SR2;
SR2
Description
The ADD instruction obtains the rst source operand from the SR1 register. The second source operand is obtained from the SR2 register. The second operand is added to the rst source operand, and the result is stored in DR.
7.3.2 NAND
Assembler Syntax
NAND DR, SR1, SR2
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
0001
DR
SR1
unused
SR2
Operation
DR = ~(SR1 & SR2);
Description
The NAND instruction performs a logical NAND (AND NOT) on the source operands obtained from SR1 and SR2. The result is stored in DR.
HINT: A logical NOT can be achieved by performing a NAND with both source operands the same. For instance,
NAND DR, SR1, SR1
...achieves the following logical operation: DR SR1.
Project 2
CS 2200 - Systems and Networks
Spring 2020
7.3.3
ADDI
Assembler Syntax
ADDI
DR, SR1, immval20
Encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0010
DR
SR1
immval20
Operation
DR = SR1 + SEXT(immval20);
Description
The ADDI instruction obtains the rst source operand from the SR1 register. The second source operand is obtained by sign-extending the immval20 eld to 32 bits. The resulting operand is added to the rst source operand, and the result is stored in DR.
7.3.4 LW
Assembler Syntax
LW DR, offset20(BaseR)
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
0011
DR
BaseR
o set20
Operation
DR = MEM[BaseR + SEXT(offset20)];
Description
An address is computed by sign-extending bits [19:0] to 32 bits and then adding this result to the contents of the register speci ed by bits [23:20]. The 32-bit word at this address is loaded into DR.
Project 2
CS 2200 - Systems and Networks
Spring 2020
7.3.5
SW
Assembler Syntax
SW
SR, offset20(BaseR)
Encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0100
SR
BaseR
o set20
Operation
MEM[BaseR + SEXT(offset20)] = SR;
Description
An address is computed by sign-extending bits [19:0] to 32 bits and then adding this result to the contents of the register speci ed by bits [23:20]. The 32-bit word obtained from register SR is then stored at this address.
7.3.6 BEQ
Assembler Syntax
BEQ SR1, SR2, offset20
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
0101
SR1
SR2
o set20
Operation
if (SR1 == SR2) {
PC = incrementedPC + offset20
}
Description
A branch is taken if SR1 and SR2 are equal. If this is the case, the PC will be set to the sum of the incremented PC (since we have already undergone fetch) and the sign-extended o set[19:0].
Project 2 CS 2200 - Systems and Networks Spring 2020
7.3.7 JALR
Assembler Syntax
JALR RA, AT
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
0110
RA
AT
unused
Operation
RA = PC;
PC = AT;
Description
First, the incremented PC (address of the instruction + 1) is stored into register RA. Next, the PC is loaded with the value of register AT, and the computer resumes execution at the new PC.
7.3.8 HALT
Assembler Syntax
HALT
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
0111
unused
Description
The machine is brought to a halt and executes no further instructions.
Project 2 CS 2200 - Systems and Networks Spring 2020
7.3.9 BGT
Assembler Syntax
BGT SR1, SR2, offset20
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
1000
SR1
SR2
o set20
Operation
if (SR1 > SR2) {
PC = incrementedPC + offset20
}
Description
A branch is taken if SR1 is greater than SR2. If this is the case, the PC will be set to the sum of the incremented PC (since we have already undergone fetch) and the sign-extended o set[19:0].
7.3.10 LEA
Assembler Syntax
LEA DR, label
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
1001
DR
unused
PCo set20
Operation
DR = PC + SEXT(PCoffset20);
Description
An address is computed by sign-extending bits [19:0] to 32 bits and adding this result to the incremented PC (address of instruction + 1). It then stores the computed address into register DR.
Project 2 CS 2200 - Systems and Networks Spring 2020
7.3.11 EI
Assembler Syntax
EI
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
1010
unused
Operation
IE=1;
Description
The Interrupts Enabled register is set to 1, enabling interrupts.
7.3.12 DI
Assembler Syntax
DI
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
1011
unused
Operation
IE=0;
Description
The Interrupts Enabled register is set to 0, disabling interrupts.
Project 2 CS 2200 - Systems and Networks Spring 2020
7.3.13 RETI
Assembler Syntax
RETI
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
1100
unused
Operation
PC = $k0;
IE=1;
Description
The PC is restored to the return address stored in $k0. The Interrupts Enabled register is set to 1, enabling interrupts.
7.3.14 IN
Assembler Syntax
IN DR, DeviceADDR
Encoding
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
1101
DR
0000
addr20
Operation
DAR = addr20;
DR = DeviceData;
DAR = 0;
Description
The value in addr20 is sign-extended to determine the 32-bit device address. This address is then loaded into the Device Address Register (DAR). The processor then reads a single word value o the device data bus, and writes this value to the DR register. The DAR is then reset to zero, ending the device bus cycle.
Project 2 CS 2200 - Systems and Networks Spring 2020
• Appendix B: Microcontrol Unit
As you may have noticed, we currently have an unused input on our multiplexer. This gives us room to add another ROM to control the next microstate upon an interrupt. You need to use this fourth ROM to generate the microstate address when an interrupt is signaled. The input to this ROM will be controlled by your interrupt enabled register and the interrupt signal asserted by the timer interrupt. This fourth ROM should have a 1-bit input and 6-bit output.
Project 2 CS 2200 - Systems and Networks Spring 2020
The outputs of the FSM control which signals on the datapath are raised (asserted). Here is more detail about the meaning of the output bits for the microcontroller:
Table 3: ROM Output Signals
Bit
Purpose
Bit
Purpose
Bit
Purpose
Bit
Purpose
Bit
Purpose
0
NextState[0]
7
DrMEM
14
LdA
21
ALULo
28
IntAck
1
NextState[1]
8
DrALU
15
LdB
22
ALUHi
29
DrData
2
NextState[2]
9
DrPC
16
LdCmp
23
OPTest
30
LdDAR
3
NextState[3]
10
DrOFF
17
WrREG
24
ChkCmp
4
NextState[4]
11
LdPC
18
WrMEM
25
TypeCmp
5
NextState[5]
12
LdIR
19
RegSelLo
26
LdEnInt
6
DrReg
13
LdMAR
20
RegSelHi
27
EnInt
Table 4: Register Selection Map
RegSelHi
RegSelLo
Register
0
0
RX (IR[27:24])
0
1
RY (IR[23:20])
1
0
RZ (IR[3:0])
1
1
$k0
