Laboratory Exercise 2 Solution

This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion and binary-coded-decimal (BCD) addition.

Part I

We wish to display on the 7-segment displays HEX1 to HEX0 the values set by the switches SW9 0. Let the values denoted by SW7 4 and SW3 0 be displayed on HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t-cares.

    1. Create a new project which will be used to implement the desired circuit on the Altera DE1 board. The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. You should use only simple VHDL assignment statements in your code and specify each logic function as a Boolean expression.

    2. Write a VHDL file that provides the necessary functionality. Include this file in your project and assign the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User Manual for the DE1 board. The procedure for making pin assignments is described in the tutorial Quartus II Introduction using VHDL Design, which is available on the DE1 System CD and in the University Program section of Altera’s web site.

    3. Compile the project and download the compiled circuit into the FPGA chip.

    4. Test the functionality of your design by toggling the switches and observing the displays.


Part II

You are to design a circuit that converts a four-bit binary number V = v3v2v1v0 into its two-digit decimal equiv-alent D = d1d0. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a VHDL entity which includes the comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point). Your VHDL entity should have the four-bit input V , the four-bit output M and the output z. The intent of this exercise is to use simple VHDL assignment statements to specify the required logic functions using Boolean expressions. Your VHDL code should not include any IF-ELSE, CASE, or similar statements.

Binary value
Decimal digits
0000
0
0
0001
0
1
0010
0
2
: : :
: : :
: : :
1001
0
9
1010
1
0
1011
1
1
1100
1
2
1101
1
3
1110
1
4
1111
1
5

Table 1. Binary-to-decimal conversion values.


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Perform the following steps:

    1. Make a Quartus II project for your VHDL entity.

    2. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multi-plexers, and circuit A.

    3. Augment your VHDL code to include circuit B in Figure 1 as well as the 7-segment decoder. Change the inputs and outputs of your code to use switches SW3 0 on the DE1 board to represent the binary number V , and the displays HEX1 and HEX0 to show the values of decimal digits d1 and d0. Make sure to include in your project the required pin assignments for the DE1 board.

    4. Recompile the project, and then download the circuit into the FPGA chip.

    5. Test your circuit by trying all possible values of V and observing the output displays.



z



d1

Comparator




0

















Circuit B
7
5
6
1














v3

m3

4

2

0



3

0
1










d0

v2
0
m2


0


1


5

1


7-segment
7

6








v1

decoder

4

2

0







m1





1



3

v0
0
m0





1





Circuit A











Figure 1: Partial design of the binary-to-decimal conversion circuit.



Part III

Figure 2a shows a circuit for a full adder, which has the inputs a, b, and ci, and produces the outputs s and co. Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum cos = a + b + ci. Figure 2d shows how four instances of this full adder entity can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of



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the way that the carry signals are passed from one full adder to the next. Write VHDL code that implements this circuit, as described below.

ci

a

b
0

1



s
ci





s

























    a FA
b





co














co



















a) Full adder circuit





b) Full adder symbol







b  a ci

co
s
b3  a3   c3
b2  a2   c2
b1  a1   c1
b0  a0  cin

















































0
0
0

0
0





































































0
0
1

0
1




































































0
1
0

0
1































0
1
1

1
0


FA




FA




FA





FA
1
0
0

0
1































1
0
1

1
0































1
1
0

1
0































1
1
1

1
1











































































cout  s3



s2



s1



s0






















c) Full adder truth table





d) Four-bit ripple-carry adder circuit









Figure 2: A ripple-carry adder circuit.




    1. Create a new Quartus II project for the adder circuit. Write a VHDL entity for the full adder subcircuit and write a top-level VHDL entity that instantiates four instances of this full adder.

    2. Use switches SW7 4 and SW3 0 to represent the inputs A and B, respectively. Use SW8 for the carry-in cin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect the outputs of the adder, cout and S, to the green lights LEDG.

    3. Include the necessary pin assignments for the DE1 board, compile the circuit, and download it into the FPGA chip.

    4. Test your circuit by trying different values for numbers A, B, and cin.


Part IV

In part II we discussed the conversion of binary numbers into decimal digits. It is sometimes useful to build circuits that use this method of representing decimal numbers, in which each decimal digit is represented using four bits. This scheme is known as the binary coded decimal (BCD) representation. As an example, the decimal value 59 is encoded in BCD form as 0101 1001.

You are to design a circuit that adds two BCD digits. The inputs to the circuit are BCD numbers A and B, plus a carry-in, cin. The output should be a two-digit BCD sum S1S0. Note that the largest sum that needs to be handled by this circuit is S1S0 = 9 + 9 + 1 = 19. Perform the steps given below.

    1. Create a new Quartus II project for your BCD adder. You should use the four-bit adder circuit from part III to produce a four-bit sum and carry-out for the operation A + B. A circuit that converts this five-bit result,

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which has the maximum value 19, into two BCD digits S1S0 can be designed in a very similar way as the binary-to-decimal converter from part II. Write your VHDL code using simple assignment statements to specify the required logic functions–do not use other types of VHDL statements such as IF-ELSE or CASE statements for this part of the exercise.

    2. Use switches SW7 4 and SW3 0 for the inputs A and B, respectively, and use SW8 for the carry-in. Connect the SW switches to their corresponding red lights LEDR, and connect the four-bit sum and carry-out produced by the operation A + B to the green lights LEDG. Display the BCD values of A and B on the 7-segment displays HEX3 and HEX2, and display the result S1S0 on HEX1 and HEX0.

    3. Since your circuit handles only BCD digits, check for the cases when the input A or B is greater than nine. If this occurs, indicate an error by turning on the green light LEDG7.

    4. Include the necessary pin assignments for the DE1 board, compile the circuit, and download it into the FPGA chip.

    5. Test your circuit by trying different values for numbers A, B, and cin.


Part V

In part IV you created VHDL code for a BCD adder. A different approach for describing the two-digit BCD adder in VHDL code is to specify an algorithm like the one represented by the following pseudo-code:


    • T0 = A + B + c0
2   if (T0 > 9) then

3Z0=10;
    • c1 = 1;
5   else
    • Z0=0;
    • c1 = 0;
8   end if
9    S0=T0    Z0
    10 S1 = c1


It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1 and 9 represent adders, lines 2-8 correspond to multiplexers, and testing for the conditions T0 > 9 requires comparators. You are to write VHDL code that corresponds to this pseudo-code. Note that you can perform addition operations in your VHDL code instead of the subtractions shown in lines 9. The intent of this part of the exercise is to examine the effects of relying more on the VHDL compiler to design the circuit by using IF-ELSE statements along with the VHDL > and + operators. Perform the following steps:

    1. Create a new Quartus II project for your VHDL code. Use switches SW7 4 and SW3 0 for the inputs A and B, respectively, and use SW8 for the carry-in. The value of A should be displayed on the 7-segment displays HEX3, while B should be on HEX2. Display the BCD sum, S1S0, on the 7-segment displays HEX1 and HEX0.

    2. Use the Quartus II RTL Viewer tool to examine the circuit produced by compiling your VHDL code. Com-pare the circuit to the one you designed in Part IV.

    3. Download your circuit onto the DE1 board and test it by trying different values for numbers A and B.


Part VI


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Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the BCD form. Use switches SW5 0 to input the binary number and 7-segment displays HEX1 and HEX0 to display the decimal number. Implement your circuit on the DE1 board and demonstrate its functionality.



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