Project 3 Solution

1. Objective
In this project, you will extend the basic MIPS processor of the previous project to build a complete processor. The single-cycle processor will execute a given subset of the MIPS instruction set. During demonstration of your project various MIPS test programs will be used for verification of your work.
2. Complete a Single-Cycle Processor
Extend the basic single-cycle processor (SCP) to support all instructions in the table.
Type
Instructions
Arithmetic (unsigned)
addu, subu, addiu, multu, divu
Arithmetic (signed)
add, sub, addi, mult, div
Logical
and, andi, or, ori, xor, xori
Shift
sll, sra, srl
Compare
slt, slti, sltu, sltiu
Control
beq, bne, blez, bgtz, j, jr, jal
Data transfer
lw, sw, lui, lb, sb
Use the actual MIPS machine language instruction formats, given in the back cover of your textbook. This project has some branch instructions and data transfer instructions as well as more ALU instructions. You need to design all control signals to take care of the additional instructions.
3.1 Extending ALU
Extend ALU capability to support more instructions, such as logical instructions, shift instructions, and compare instructions. Since these instructions are either R-type or I-type, just extend the controller and ALU without any additional module.
3.2 Supporing Control Instructions
In the previous project, PC was always incresing by 4. However, if the instruction fetched from the instruction memory is a control instruction, the behavior of PC is different. When the instruction is a branch instruction, the next value of PC is either PC + 4 if the branch is not taken or PC + 4 + offset if the branch is taken. The offset is coming from imm16. One mux is required to control the value of PC. Since the branch instruction is not always taken, the mux must be controlled by an output of ALU named Zero as well.
Unlike branch instructions, jump instructions are always taken and the target address is nearly fully provided in the instructions. Thus, another mux is required to control the value of PC. This mux selects the jump address if the instruction is a jump instrution.
3.3 Supporting Data Transfer Instructions
Usually, data transfer instructions use indirct address mode, which requires addition to calculate the address. Once the address is determined, it is fed into DataMem. If the instruction is a store instruction, the written value must come from the register file and is fed to Datamem. If the instruction is a load instruction, there is an output from Datamem going to the register. Since ALU has an output going to the register file, one mux is needed to select a write data to the register file.
3. Testing and Diagnostic Programs
A simple diagnostic program is provided in imeminit.v. You need to run the program using your processor and display the all internal states of a module by using appropriately coded $display("..."); statements from within the module.
Check-off Requirement: Show your solution to TA and demonstrate program execution in VCS.

Submission Requirement
Turn in your Verilog code and simulation results with the test program provided. You also need to submit a report about your design. For example, you need to show truth tables for all control signals you are using in the project.

Acknowledgement: This project was developed by Dr. Michael E. Thomadakis.