Project 05 Solution

IMPORTANT!




Please follow the submission guidelines below or your submission will be rejected.




You are expected to submit both a lab report and the source files to Blackboard in a single submission attempt.



The source codes must be under a single project.



The VHDL project needs to be exported from Xilinx ISE Design Suite. To export VHDL project file, please refer to Blackboard - Content - Lab - Exporting VHDL Project Files.



Naming convention:
Report: “FirstName_LastName_Project_XX_MMY.pdf”




Project: “FirstName_LastName_Project_XX_MMY.zip”




Replace “XX” and “Y” with the actual project number and section number, respectively.













In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) 14.7 to complete the following tasks.




Please read the instructions carefully. Failing to follow the instructions would lead to significant point deductions.




Task 1: Counting 1s from two inputs (11 points)




In the homework assignment of Chapter 7, you are asked to design a clocked synchronous state machine to count the number of 1s from two inputs. The circuit has two binary inputs, X and Y, and one binary output, Z. It counts the total number of 1s from X or Y. If the number of 1 inputs on X and Y is a multiple of 4 (e.g., 0 or 4), the output is “1”, otherwise the output is “0”. When the output is “1”, a new 1 from either X or Y (or both) will reset the output to “0”.




Using structural design, implement the clocked synchronous state machine using VHDL. Please adopt the following entity declaration.



















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Once you have the module implemented, use the test-bench program listed below and run simulations to validate your design.















































































































































































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Requirement(s):

In your VHDL implementation




- Please follow the structural design method;




Deliverable(s):




Your report:




Use your own language to describe the function of the module to be implemented in VHDL. (1 point)



Draw a circuit diagram of the module to show the design. (2 point)
Include your VHDL architecture definition(s). (1 point)
Show the RTL schematic of the module. (1 point)



Show simulation results (e.g. the waveforms). Include the outcome of each testcase with screenshots. Explain why your simulation result is correct. (2 points)



Your project file(s):

Can compile without any errors. (2 point)
Can run simulations without any errors. (2 point)



Note: no points will be given if requirements are not satisfied.



















Task 2: Behavioral Design (9 points)







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Repeat Task 1 but use a behavioral design. You can use the same test bench to run simulations and validate your implementation.




Requirement(s):




In your VHDL implementation

- Please follow the behavior design method;




Deliverable(s):







Your report:

Use your own language to explain how the circuit works. (1 point)



Include your VHDL entity declaration(s) and architecture definition(s). (1 point)



Show the RTL schematic of the module from Xilinx. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (2 points)



Your project file(s) should:

Compile without any errors. (2 point)
Run simulations without any errors. (2 point)



Note: no points will be given if requirements are not satisfied.

































































































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