Logic Design Lab 1

    • Introduction

This laboratory aims to get you familiar with basic logic gates and combinational circuit design. You will simplify the circuit that is explained below and draw the circuit using Logisim tool with the given gates.


    • IC Pool

74LS04 (Inverter) 74LS08 (AND)

74LS32 (OR)


    • Lab Work

In this assignment, you are expected to perform the operations described in the following section.

3.1    Speci cations

Suppose A and B are 2-bit binary input numbers and X, Y and Z are 1-bit binary output numbers. A and B are represented with A1, A0, B1 and B0 bits respectively where A1 and B1 are the most signi cant bits and A0 and B0 are the least signi cant bits of the relevant number. Your circuit will take A and B as inputs and give the outputs X,Y and Z with the following instructions:

(
    • A+B>2
    • =
    • otherwise
(
1    A    mod B = 1
    • =
    • otherwise
(
    • (A   B)>(B   A)
    • =
    • otherwise


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You have to use "input pins" and "output pins" for your inputs and outputs, respectively, from the Toolbar at the top of Logisim. Set their labels correctly using the following names. Please, only set \label" property of the \pin" objects, do not add a \label" object onto the Logisim canvas.

Input pins: A1, A0, B1, B0.

Output pins: X, Y, Z.

Each pin corresponds to a digit in a 2-bit binary number. If it is set, then the value of the digit is 1 if reset, then the value of the digit is 0.

Note that A mod B is not unde ned when B is 0, because modulation is not division. You are trying to nd out what remains.The result will simply be A when B is 0.



3.2    Input Output Examples

    1. Suppose A1A0 = 00 and B1B0 = 10. In this case, A=0 and B=2 in decimal. A+B=2

Since A + B > 2 does not hold, the output X is 0.

    2. Suppose A1A0 = 10 and B1B0 = 01. In this case, A=2 and B=1 in decimal. A+B=3

Since A + B > 2 holds, the output X is 1.

    3. Suppose A1A0 = 01 and B1B0 = 01. In this case, A=1 and B=1 in decimal. A mod B = 0

Since A mod B = 0, the output Y is 0.

    4. Suppose A1A0 = 01 and B1B0 = 10. In this case, A=1 and B=2 in decimal. A mod B = 1

Since A mod B = 1, the output Y is 1.

    5. Suppose A1A0 = 01 and B1B0 = 10. In this case, A=1 and B=2 in decimal. A B = 4 and B A = 4

Since (A   B) == (B   A), the output Z is 0.

    6. Suppose A1A0 = 01 and B1B0 = 11. In this case, A=1 and B=3 in decimal. A B = 8 and B A = 6

Since (A   B) > (B   A), the output Z is 1.


    • Free Session

There will be a "free session week" starting from February 25 till February 28 (Your speci c session will be announced later). You will have 2 hours in your free session slot. During the free session, you will try to build your circuit on a breadboard by using IC components, and you will practice how to handle possible problems related to physical circuit.


    • Demo Session

There will be a 2-hour-long "demo session week" following the free session week. In demo session:

You will take a short quiz about the logic concepts that involve the coverage of this lab.


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You will reconstruct your circuit on your breadboard.

You will show that the circuit drawn in Logisim works as speci ed.


    • Deliverables

        1. Submit the circuit named e1234567.circ prepared in Logisim, which is your preliminary work, until the speci ed deadline. Do not forget to replace e1234567 with your 7-digit student ID. The evaluation of the submission will be a black-box test. You should use CENG version of Logisim which is available on ODTUClass course page. Circuits designed with other Logisim versions, other tools or not named properly will not be graded!

        2. In demo session, you will reconstruct and show that the circuit drawn in Logisim works. This part will be graded in lab. Please note that submission of a working circuit is a must to attend DEMO lab sessions.


    • What to Bring in the Lab

Print-out submitted  le of the circuit.

Lab materials and data-sheets of chips. www.alldatasheet.com

Pencil and eraser, as you will have a quiz at the very beginning of the DEMO lab.


    • Cheating Policy

All the lab work should be individual and there is zero tolerance policy for cheating. See the course website for further information about cheating policy.


    • References

CENG Logism Version.


























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