In this project, you will use Altera Quartus II with Verilog. You will design a part of the 32-bit MIPS processor. The block that you will design will get an 32-bit instruction as its input and compute the resultant value and stores it to the destination register given by the instruction. The only supported instructions in your design will be add, addu, sub, and, or, sra, srl, sll, sltu instructions. The input of your top-module will be the instruction only. The output of your top-module will be the output of your ALU to follow and check its computations during the simulation. You can write the register contents using writememh in your testbench verilog code. You can display memory contents using readmemh.
1. Use behavioral Verilog wherever needed.
2. You will design Register module using behavioral Verilog. The register has 32 registers
each containing 32-bit number.
3. You will write one top-level Verilog module to connect ALU and Register modules accurately to finish the project.
4. You will write a working testbench and simulate your design by ModelSim as you
learnt in the PS.
5. The top module should exactly look like this:
32
32 bit
TOP MODULE
32-bit 32
instruction
ALU Out
6. Attend the PS to understand the project well.
7. (Advanced Students) Successful testing the R-type MIPS on DE0 Board will give you
30pts bonus.
Your design should not support I-type or J-type instructions. Only the instructions listed above.
Please be sure that your design simulates correctly. Designs that are not even simulating can get at most 20 points.
Submit your Altera Project folder as a zip file to Moodle. We will simulate your design using not only your testbench but also our testbench to see whether all instructions are executing correctly or not.
