Lab 6 Solution

0. Objective
This laboratory assignment introduces Verilog, a Hardware Description Language (HDL) and shows you how to model and simulate basic combinational circuits and classic memory elements. HDLs are used extensively in the process of designing and implementing digital computer hardware components such as ALU and registers.
Note: All Verilog codes submitted must be able to run with VCS. The department Sun machine is accessible from the Internet.

1. Implementing a simple Boolean function [0 point]

Circuit Diagram of ab + ~a
Step 1: Using primitive Verilog gates, we implement the Boolean function, ab + ~a shown in the figure above. The following Verilog code has two modules: first_module and test_first. first_module has two inputs (a, b) and has one output (out) for the Boolean function. test_first is a test bench module that examines the output of first_module with different inputs. The test bench module is used to generate test cases only.
Do not implement your design in the test bench.
module first_module(out, a, b);
    input    a, b;
    output   out;
    wire     a1, a2;

    not    n1(a1, a);
    and    and1(a2, a, b);
    or     or1(out,a1,a2);
endmodule

module test_first();              /* test bench module for first_module() */
    reg    a, b;
    wire   out;

    first_module fm(out,a,b);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tout=%b",a,b,out);
        a = 0; b = 0;
        #1 
        a = 0; b = 1;
        #1
        a = 1; b = 0;
        #1
        a = 1; b = 1;
        #1 
        $finish;
    end
endmodule
Please name all wires before implementation. Copy this code into the text editor (vi or emacs) and save the file as lab6_1.v.
Step 2: Now you have a complete Verilog model, ready for testing. We compile and run above code with VCS. Use the following Unix command in the department Sun machine (sun.cs.tamu.edu)
$ vcs -R lab6_1.v
You should get the following output in the window. If you do not, then you probably have one or more typing errors in your input file. Correct them, and try again. Note that there is a semi-colon at the end of the module statement.
*** Using loader /usr/ccs/bin/ld instead of cc ...
                         Chronologic VCS (TM)
          Version Y-2006.06-SP1 -- Mon Feb 10 12:00:00 2008
               Copyright (c) 1991-2006 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'lab6_1.v'
Top Level Modules:
       test_first
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module test_first because:
        This module or some inlined child module(s) has/have been modified.
if [ -x ../simv ]; then chmod -x ../simv; fi
/usr/ccs/bin/ld  -o ../simv  /opt/apps/synopsys/vcs/sparcOS5/lib/crt1.o
/opt/apps/synopsys/vcs/sparcOS5/lib/crti.o
5NrI_d.o 5NrIB_d.o P0Zc_1_d.o SIM_l.o  
/opt/apps/synopsys/vcs/sparcOS5/lib/libvirsim.a -lnsl -lsocket -ldl    
/opt/apps/synopsys/vcs/sparcOS5/lib/libvcsnew.so 
-lm -lc  -ldl  /opt/apps/synopsys/vcs/sparcOS5/lib/crtn.o
../simv up to date
Chronologic VCS simulator copyright 1991-2005
Contains Synopsys proprietary information.
Compiler version Y-2006.06-SP1; Runtime version Y-2006.06-SP1;  Feb 10 12:00 2008

                   0    a=0     b=0     out=1
                   1    a=0     b=1     out=1
                   2    a=1     b=0     out=0
                   3    a=1     b=1     out=1
$finish at simulation time                    4
           V C S   S i m u l a t i o n   R e p o r t
Time: 4
CPU Time:      0.140 seconds;       Data structure size:   0.0Mb
Mon Feb 10 12:00:00 2008
CPU time: 0 seconds to compile + 0 seconds to link + 0 seconds in simulation
Use "-R" option if you want to run your code after compilation. Without "-R" option, you need to run the compiled executable code separately. The compiled executable code is saved as "simv" without "-o" option. However, you can specify the output file name with "-o" option.
You can find more information about VCS here.
Check-off Requirement: No

2. Half Adder [10 points]
A half-adder is a combinational circuit that adds two 1-bit inputs (A and B), and generates 1-bit sum (S) and 1-bit carry (C). The truth-table and the circuit diagram for the half-adder are shown below:
A
B
S
C

0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
 

(a) Truth Table
(b) Circuit Diagram

Structurally define a half-adder and prepare a proper test bench to test the half-adder. Save your code as "lab6_2.v" and evaluate your design with VCS. Test this module completely since you will be using it as a building block for the full-adder. Show the results of the all possible cases in the truth-table.
Check-off Requirement: Show your solution to TA and demonstrate program execution in VCS.

3. Full Adder composed of NAND Gates Only [20 points]
Structurally define a 1-bit full adder using NAND gates only. The truth table for the full-adder and the schematic with two half adders are shown below:
A
B
Cin
S
Cout


0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
 

(a) Truth Table
(b) Circuit Diagram



(c) Circuit Diagram of NAND-only Full Adder
Prepare a proper test bench to test the full-adder. Save your code as "lab6_3.v" and evaluate your design with VCS. Test this module completely since you will be using it as a building block for your multi-bit adders. Show the results of the all possible cases in the truth-table.
Check-off Requirement: Show your solution to TA and demonstrate program execution in VCS.

4. Multi-bit Ripple Carry Adder [20 points]
Your designs so far have been single bit with 1-bit ports, wires and registers. To model multi-bit objects, you may specify the size when declaring the object. For example, a 4-bit wide wire can be declared as:
        wire [3:0] S;
In the same way, 4-bit wide registers can be declared as:
        reg [3:0] A, B;
The same may be done for inputs and outputs. You can also access the individual bit lines or a sub-group of the bit-lines.
        A[0]    // The least significant bit in A
        A[3:2]  // The two most significant bits in A
Develop a 4-bit ripple carry adder using multi-bit declarations with the 1-bit full-adder you developed earlier. Prepare a proper test bench for this new module. Save your code as "lab6_4.v" and evaluate your design with VCS.
The circuit diagram of the 4-bit ripple carry adder is shown below.

4-bit Ripple Carry Adder Circuit Diagram
Check-off Requirement: Show your solution to TA and demonstrate program execution in VCS with the following cases. Printing input/output numbers in the test bench must be formatted in a decimal format.
Case #
A
B
C0
1
0
0
0
2
0
0
1
3
0
1
0
4
1
0
0
5
1
1
0
6
1
1
1
7
7
7
0
8
7
7
1
9
15
0
0
10
15
0
1
11
15
1
0
12
15
1
1
13
0
15
0
14
0
15
1
15
1
15
0
16
1
15
1
17
15
15
0
18
15
15
1
Table: Test Cases in 4-bit adders
Use the following code in your test bench for the test cases in 4-bit adders
        initial begin
                $monitor($time, "\tA=%d\tB=%d\tCin=%b\tS=%d\tCout=%b", A, B, C0, S, Cout);
                
                A = 0;  B = 0;  C0 = 0;
                #1
                A = 0;  B = 0;  C0 = 1;
                #1
                A = 0;  B = 1;  C0 = 0;
                #1
                A = 1;  B = 0;  C0 = 0;
                #1
                A = 1;  B = 1;  C0 = 0;
                #1
                A = 1;  B = 1;  C0 = 1;
                #1
                A = 7;  B = 7;  C0 = 0;
                #1
                A = 7;  B = 7;  C0 = 1;
                #1
                A = 15; B = 0;  C0 = 0;
                #1
                A = 15; B = 0;  C0 = 1;
                #1
                A = 15; B = 1;  C0 = 0;
                #1
                A = 15; B = 1;  C0 = 1;
                #1
                A = 0;  B = 15; C0 = 0;
                #1
                A = 0;  B = 15; C0 = 1;
                #1
                A = 1;  B = 15; C0 = 0;
                #1
                A = 1;  B = 15; C0 = 1;
                #1
                A = 15; B = 15; C0 = 0;
                #1
                A = 15; B = 15; C0 = 1;
                #1
                $finish;
        end


5. Decoder and Multiplexer [20 points]
(1) Design and structurally define a 3x8 decoder and a 1-bit full adder in Verilog using a decoder as a basic building block. Use the 3x8 decoder you developed to replace the full adder. Prepare a proper test bench module to test all possible cases and evaluate your design. Save your code as "lab6_5dec.v" and run it with VCS.
(2) Design and structurally define a 4x1 multiplexer and a 1-bit full adder in Verilog using two multiplexers as a basic building block. Use the 4x1 multiplexer you developed to replace the full adder. Prepare a proper test bench module to test all possible cases and evaluate your design. Save your code as "lab6_5mux.v" and run it with VCS.
The following figure shows how to define a full-adder using a decoder or two 4x1 multiplexers.

Full Adder Implemented by a Decoder and two Multiplexers
Check-off Requirement: Show your solution to TA and demonstrate program execution in VCS.

6. 32-bit Ripple Carry Adder [30 points]
Design and structurally define a 32-bit adder using a 4-bit full adder you developed in Part 4 and prepare a proper test bench Save your code as "lab6_6.v" and evaluate your design with VCS.
Check-off Requirement: Show your solution to TA and demonstrate program execution in VCS with the following cases. Printing input/output numbers in the test bench must be formatted in a decimal format.
Case #
A
B
C0
1
0
0
0
2
0
0
1
3
0
1
0
4
1
0
0
5
1
1
0
6
1
1
1
7
16777215
16777215
0
8
16777215
16777215
1
9
4294967295
0
0
10
4294967295
0
1
11
4294967295
1
0
12
4294967295
1
1
13
0
4294967295
0
14
0
4294967295
1
15
1
4294967295
0
16
1
4294967295
1
17
4294967295
4294967295
0
18
4294967295
4294967295
1
Table: Test Cases for 32-bit adders
Use the following code in your test bench for the test cases in 32-bit adders
        initial begin
                $monitor($time, "\tA=%d\tB=%d\tCin=%b\tS=%d\tCout=%b", A, B, C0, S, Cout);
                
                A = 0;          B = 0;          C0 = 0;
                #1
                A = 0;          B = 0;          C0 = 1;
                #1
                A = 0;          B = 1;          C0 = 0;
                #1
                A = 1;          B = 0;          C0 = 0;
                #1
                A = 1;          B = 1;          C0 = 0;
                #1
                A = 1;          B = 1;          C0 = 1;
                #1
                A = 16777215;   B = 16777215;   C0 = 0;
                #1
                A = 16777215;   B = 16777215;   C0 = 1;
                #1
                A = 4294967295; B = 0;          C0 = 0;
                #1
                A = 4294967295; B = 0;          C0 = 1;
                #1
                A = 4294967295; B = 1;          C0 = 0;
                #1
                A = 4294967295; B = 1;          C0 = 1;
                #1
                A = 0;          B = 4294967295; C0 = 0;
                #1
                A = 0;          B = 4294967295; C0 = 1;
                #1
                A = 1;          B = 4294967295; C0 = 0;
                #1
                A = 1;          B = 4294967295; C0 = 1;
                #1
                A = 4294967295; B = 4294967295; C0 = 0;
                #1
                A = 4294967295; B = 4294967295; C0 = 1;
                #1
                $finish;
        end

Submission Requirement
Turn in all of your source code. (lab6_2.v lab6_3.v lab6_4.v lab6_5dec.v lab6_5mux.v lab6_6.v)