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Lab 5: FIR Filter Design Solution
• Introduction
A digital FIR Filter is basically a set of MAC operations specified in an order depending upon on the nature of the filter. We will be designing an 8-tap filter in this lab. The filter equation is
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y[n] = h[i]x[n − i]
i=0
Here, the coefficients h[i] have real and imaginary parts, both of which are 8-bit signed fix-
point numbers and are hard-coded in the design. Also, note that the multiplication and addition are signed operations. The template for the FIR filter is provided in filter_8.vhd in ./src
directory.
The explanations of the input and output ports are given below.
• clk => Clock signal. We use rising edge for flops.
• rst => Reset signal. Note that the sequential elements that are used in your design should have synchronous active high reset. i.e. if the reset is pulled high, the flops should be reset at next rising edge of clk.
• in_valid => in_valid is the qualifier for the data. When in_valid = 1, the data at the same cycle is valid.
• next_in => next_in is generated by the design and tells the testbench that, if next_in = 1, the testbench can feed next data set, otherwise the testbench has to hold the current valid data.
• data_in => The input data port from which data is passed to the design. Note that the real 8-bit fix-point data is passed to the design serially.
• data_real_out and data_imag_out => Outputs from the design. After the complex op-erations, the real data which is passed into the input is transformed into real and imaginary components.
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• out_valid => valid signal for the output. When out_valid = 1, the outputs data_real_out and data_imag_out are valid. This information is useful to the testbench which captures the data only when output is valid.
• next_out => next_out is generated by the testbench and tells the design that, if next_out = 1, the design can generate next output data set, otherwise the design has to hold the current valid data.
data_in
in_valid
next_in
0
1
2
3
4
5
6
7
coef_real(0)
coef_real(1)
coef_real(2)
coef_real(3)
coef_real(4)
coef_real(5)
coef_real(6)
coef_real(7)
coef_imag(0)
coef_imag(1)
coef_imag(2)
coef_imag(3)
coef_imag(4)
coef_imag(5)
coef_imag(6)
coef_imag(7)
Complex
Complex
Complex
Complex
Complex
Complex
Complex
Complex
Mult
Mult
Mult
Mult
Mult
Mult
Mult
Mult
Complex
Complex
Complex
Complex
Add
Add
Add
Add
Complex
Complex
Add
Add
Complex
Add
right shift by 9
next_out out_valid data_real_out
data_imag_out
Figure 1 8-tap FIR filter with real data and complex coefficients
This system can be implemented in numerous ways with different latencies, area and power. You can use any architecture as long as you can clearly draw the block diagram of your archi-tecture in the report.
There is an input file input_seq.txt from which the data is read into the testbench, as well as an input file input_out_ready.txt from which the next_out is to be assigned. The testbench dumps out an output file. Compare this output with the reference output file output_ref.txt
provided with the assignment. The output will be the same for any architecture. The grad-ing will take into consideration the functional correctness, utilization (area), timing and the
power of the design. Three re-submissions are allowed for this lab. The resources informa-tion is obtained from filter_8_utilization_placed.rpt. The timing information is ob-tained from filter_8_timing_summary_routed.rpt. The power information is obtained from filter_8_power_routed.rpt.
Note that our design may be very bad for area but is quick. So the testbench gives a data sample every cycle, if possible. In your design, you can choose to use a memory/buffer which stores all these samples and will parse it to main logic at a speed which is decided by the latency of your architecture. This additional memory overhead will not be considered for grading.
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• Instructions
1. Draw the block diagram of the architecutre you will be using. (If you are using the same architecture as the figure above, then you don’t need to draw it)
2. Complete your design in VHDL. You can use multiple design files this time, but the top file should be filter_8.vhd.
3. Run the simulation for filter_8.vhd using the provided testbench tb_filter_8.vhd to match your output file output.txt with the reference output_ref.txt.
4. Run the synthesis and implementation of your design filter_8.vhd in Vivado using the provided constraint file constraints.xdc.
• Deliverables
1. Create a PDF report containing:
▪ Block diagram of your design (If you are using the same architecture as the figure above, then you don’t need to draw it)
▪ Tables of
(a) Resources (Only “Slice Logic”, “IO and GT Specific”, “Primitives”) from filter_8_utilization_placed.rpt
(b) Power (Dynamic and Static) from filter_8_power_routed.rpt
(c) Worst Negative Slack (“Design Timing Summary”) from filter_8_timing_summary_routed.rpt
▪ (15% of grade) Answer the question: Why do you think we need to do right shift operation? And why do we do it at the end? (Answer should not exceed 6 sentences)
The name of the PDF should be of the form lab5_firstname_lastname.pdf , e.g.
lab5_george_burdell.pdf .
2. (75% of grade for this bullet and the next) The completed design file filter_8.vhd . (No latch generated; synchronous reset, sensitivity signal list correct)
3. Other modules (if applicable)
4. The simulated output file output.txt in the “run” folder.
5. (10% of grade) The implemented area (utilization), power and timing reports, namely, filter_8_utilization_placed.rpt
filter_8_power_routed.rpt
filter_8_timing_summary_routed.rpt
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Move all of these files into a folder called lab5_firstname_lastname_gtID . Zip the folder and upload the archive lab5_firstname_lastname_gtID.zip on T-Square (eg. lab5_george_burdell_123456789.zip ). The first name and last name should be all in lower
case. Please strictly follow this naming convention. Otherwise my script will not work and you might get points deduction.
Note: Late submissions are not accepted. In case of extraordinary circumstances, writ-ten permission must be obtained from Dr. Madisetti.
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