Lab 02 Solution

Problem 1:




Draw and Verify



F = abc + ab + a + b + c



G = a’b’c + ab’c + abc



What are the names of the 74xx series logic gates that you should use?



For the four “or” gates you can use the 74x32 gate which has quad 2-input “or” gates. For the two “and” gates you can use a 74x08 since this have quad 2-input “and” gates.



For the two inverters that you would need you can use a 74x04 which is a hex inverter gate. For the two “and” gates you can use a 74x08 which has quad
2-input “and” gates. For the four “or” gates you can use a 74x32 which has quad 2-input “or” gates.




Calculate the delay performance, assume you have used 74Fxx or 74LSxx series gates.



When all the inputs (a, b, and c) are set to 1, all the gates are used. This is because when all inputs are set to 1 the output is 1. This means all 6 gates are used (2 “and” gates and 4 “or” gates). They maximum delay would be 4.2 * 6 = 25.2ns (the “or” and “and” gates have the same gate delay)



The longest path would be when input a and c are set to 1. This would use 6 gates and 1 inverter. The 6 gates has a delay of 4.2 * 6 = 25.2ns and the inverter has a delay of 3.7 ns. This total would be 28.9 ns.



Which data sheet parameters did you use to calculate.



The data sheet parameters that I used were the typical propagation delays measured at 25 degrees celsius. This is the average delay at that temperature. Gate delay tends to increase with temperature but the manufacturer chose to display 25 degrees celsius because that is the common operating temperature of the gate. This was chosen for all two of the gate types and the inverters.



74F32 - quad “or” gate



Propagation delay (Typical 4.2ns), From input to output (Typical 4.0ns)



https://pdf1.alldatasheet.com/datasheet-pdf/view/50329/FAIRCHILD/74F3 2.html



74F08 - quad “and” gate



Propagation delay (Typical 4.2ns), From input to output (Typical 4.0ns)



https://pdf1.alldatasheet.com/datasheet-pdf/view/179285/FAIRCHILD/74F 08.html



74F04 - hex “inverter” gate



Propagation delay (Typical 3.7ns), From input to output (Typical 3.2ns)



https://pdf1.alldatasheet.com/datasheet-pdf/view/50274/FAIRCHILD/74F0 4.html



Problem 2:




1. Identify design parameters -

Number of switches: There should be 7 switches, 1 for the engine and then 6 for the cars that follow it.



Number of bits/wires required in the data bus: There should be 3 bits.



Size of encoder/decoder:



The encoder should be 8x3 meaning it takes 8 inputs and turns it into 3 outputs



The decoder should be 3x8 meaning it takes 3 inputs and turns it into 8 outputs



Read the 7 segment LED display datasheet



The way that the 7 segment display works is that it has 8 parts to it. It also has 8 input pins. Each of the input pins is mapped to a segment on the 7 segment display. Often time the display will have an 8th segment that is for the decimal which would allow multiple 7 segment display to be put together to create larger numbers. The 7 segment display can display the numbers 1-9 by using the correct input pins to light certain segments of a number.



Design the encoder and decoder blocks with basic logic gates the do it is logisim



a.




C0
C1
C2
C3
C4
C5
C6


O1
O2
O3






















1
0
0
0
0
0
0


0
0
1






















0
1
0
0
0
0
0


0
1
0






















0
0
1
0
0
0
0


1
0
0






















0
0
0
1
0
0
0


1
1
0






















0
0
0
0
1
0
0


0
1
1






















0
0
0
0
0
1
0


1
0
1






















0
0
0
0
0
0
1


1
1
1






















b.




Brief explanation



Encoder Design: The way that the encoder works is that it takes input in from the user through 7 buttons. Each of these buttons would be located in a different train car with 0 being the driver’s car and 1-6 being the respective cars following the driver. If a user was to press their button in their car the respective number would light up for the driver. By default the number 0 is shown. The way the encoder works is that it takes the button press and based on the respective number it converts that into a 3 digit binary combination that is output and is carried to the decoder.



Decoder Design: The way that the decoder works is that it takes from the bus 3 inputs that is a binary combination of 3 bits. This then takes those three inputs
and passes them through respective “and” gates that decide which number the 3 bits actually represent (0-6). Now that we have converted the 3 bit combination to a singular decimal number between 0 and 6. This number is then decoded to its different segments. This means that we take the respective numbers and we decide which of the 7 segments must be turned on to display that number. We do this using “or” gates that are mapped to inputs on the 7 segment display.




On a high level it takes in a user button press and turns on respective portions of a 7 segment display to show the number that is being passed in.