ECEN Lab 9: BJT Amplifier Design

Objectives

The purpose of this experiment is to design a multi-stage BJT amplifier based on a list of specifications.

Introduction

Design of an amplifier typically requires multiples of stages to satisfy all specifications, so a system-level evaluation of the requirements is necessary to determine how many and what type of stages will be needed. Based on the gain and output swing requirements, the number of gain stages can be estimated. Depending on the load resistor, adding a buffer may become necessary to preserve the gain. If performed accurately, the initial assessment may be sufficient to determine the overall topology, but it usually takes a few iterations to complete the design.

Figure 1 shows two versions of two-stage amplifiers composed of a gain stage and a buffer. Assuming Ri2 RC , the maximum available gain for these circuits can be determined as VRC =VT when RG is zero. The gain can always be reduced by increasing RG , but cannot be increased beyond Av,max = VRC ,max =VT , where VRC ,max = VCC VRE
^    j    j. Therefore, if the gain specification is higher than    , an extra gain stage is needed. The buffer
Vo    VCE ,sat    Av,max
stage is usually necessary when the load resistor is small, i.e., a few hundreds of ohms or smaller. Driving such a low resistance directly from the amplifier stage significantly reduces the gain or requires a gain stage with a very high power dissipation.

Figure 1: Two-stage BJT amplifier

Assuming that one gain stage followed by a buffer is sufficient for the design requirements, the circuits in Fig. 1 can be used as a starting point. Typical specifications include, but not limited to:

0-to-peak output swing: ^ Vo

Gain: Av = Av1Av2 (where Av1 is the amplifier gain and Av2 is the buffer gain)

Input resistance: Ri

Load resistance: RL

Linearity: v^be1     VT

-insensitivity: IRB1     IB1, IC 1     IB2

VBE -insensitivity: VRE    0.1V

Using one of the circuits in Fig. 1, the design procedure can be given as follows:

    • Assume Av2 1 and Ri2 RC , which is necessary to make the overall gain insensitive to , as Ri2 is directly dependent on .

    • Choose VRE 0.1V , which requires VRE 1V . Smaller values of VRE cause the DC biasing to be sensitive to variations of VBE , whereas larger values decrease the available output swing.


c    Department of Electrical and Computer Engineering, Texas A&M University

1
    • Since the buffer gain Av2 is assumed to be close to unity, the AC signal magnitudes at the output, at the emitter of Q2, and at the collector of Q1 will be similar, where the main difference among these voltages will be their DC levels. To avoid voltage clipping, VRC should be chosen such that

^
VRE  j
^
VCC    Vo

VCE ,sat j  VRC    Vo
To maximize the available gain and linearity, VRC should be maximized, however the value of jVCE ,sat j can be chosen slightly larger (0.3 to 0.5V) than the typical value of 0.2V to account for variations in the circuit, as well as the small AC signal content at VRE .
í The output voltage is a sine wave with the amplitude ^ , therefore the maximum value of    in Fig. 1 is
Vo    IL
^    . When    reaches its maximum level, the voltage drop on    reaches its minimum. Since    is always a
Vo =RL    IL    RH    IE 2
positive current (leaving the emitter for NPN, or entering the emitter for PNP), the current on RH must always be larger than IL to avoid current clipping. Therefore, RH should be chosen such that

VRC
^


^

0.7  Vo


Vo


RH


RL
Once RH is chosen, IC 2 can be determined from






IC 2
=
VRC
0.7




RH











    • The maximum value of IC 1 is determined by the input resistance requirement, whereas the minimum value of IC 1 depends on IB2, since for -insensitive design IC 1 IB2 is required. Therefore, IC 1 should be chosen such that
N
IC 2
IC 1





1







Ri


N
+
N

+
jAv j






VRE + 0.7

VCC    VRE












0.7   VRC

where N    10.

    • Calculate the resistor values:


































































í




















v2






i2



e2



L






re2
+ (RH k RL)













í Further adjustments can be done after simulation. RB1 and RB2 can be re-adjusted for DC biasing, whereas RG can be used to fine-tune Av and Ri . RH may also be modified (typically decreased) in case of current clipping at the buffer.

Calculations

Design a BJT amplifier based on the specifications provided in the table below. Your design should be insensitive to variations, and both the input and the output should be AC coupled as in Fig. 1.

Supply Voltage, VCC
5V
Load Resistance, RL
100 
Transistor’s Current Gain,
100
Relative Variation of IC for VBE = 0.7  0.1V
10%
^
1V
0-to-Peak Output Swing, Vo

Voltage Gain, jAv j
20
Input Resistance, Ri
1k
THD for 5kHz 1V (0-to-peak) Sine Wave Output Voltage, Vo
5%




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Simulations

For all simulations, provide screenshots showing the schematics and the plots with the simulated values prop-erly labeled.

    1. Draw the schematics of the amplifier you designed, and obtain the DC solution for all node voltages and branch currents using DC operating point or interactive simulation. Adjust your component values if the results are significantly different from your calculations.

    2. Obtain Av and Ri using AC simulation. If necessary, adjust the resistor values to satisfy the specifications.

    3. Apply a 5kHz 50mV sine-wave input and obtain the time-domain waveforms at the input and the output using transient simulation. If your output voltage is clipped or significantly distorted, adjust your design values until you have unclipped 1V (0-to-peak) output signal, while keeping Av and Ri requirements satisfied.

    4. With the 5kHz 50mV sine-wave input, obtain the total harmonic distortion (THD) on the output waveform using Fourier simulation.

Measurements

For all measurements, provide screenshots showing the plots with the measured values properly labeled.

    1. Build your amplifier using the simulated component values, and measure DC voltages at all nodes using the voltmeter or scope.

    2. Measure Av and Ri using the network analyzer. If necessary, adjust the resistor values to satisfy the specifica-tions.

    3. Apply a 5kHz 50mV sine-wave input and obtain the time-domain waveforms at the input and the output using the scope. If your output voltage is clipped or significantly distorted, adjust your design values until you have unclipped 1V (0-to-peak) output signal, while keeping Av and Ri requirements satisfied.

    4. Apply a 5kHz 50mV sine-wave input and obtain the total harmonic distortion (THD) on the output waveform using the spectrum analyzer.

Report

    1. Include calculations, schematics, simulation plots, and measurement plots.

    2. Prepare a table showing calculated, simulated and measured results.

    3. Compare the results and comment on the differences.

Demonstration

    1. Build the two-stage amplifier you designed on your breadboard and bring it to your lab session.

    2. Your name and UIN must be written on the side of your breadboard.

    3. Submit your report to your TA at the beginning of your lab session.

    4. Measure Av and Ri of the amplifier using the network analyzer.

    5. Apply a 5kHz 50mV sine wave input and show the time-domain output voltage using the scope.

    6. With the 5kHz 50mV sine wave input, measure the THD at the output using the spectrum analyzer.








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