ECEN Lab 10: Characterization of the MOSFET Solution

Objectives

The purpose of this lab is to characterize N and P type metal-oxide-semiconductor field-effect transistors (MOS-FETs), also known as NMOS and PMOS transistors.

Introduction

Figure 1 shows typical symbols for the NMOS and PMOS transistors. Depending on the applied DC bias, MOSFETs have three regions of operation:

Cutoff Region:

NMOS: VGS < Vtn  ) ID = 0

PMOS: VSG < Vtp  ) ID = 0

Triode (Linear) Region:
NMOS: VDS < Vov
) ID = kn0
W
Vov VDS

V 2

,
Vov = VGS
Vtn



L

2













DS





PMOS: VSD < Vov
) ID = kp0
W
Vov VSD
V 2

,
Vov = VSG  j
Vtpj




L

2













SD







Active (Saturation) Region:


(a)    (b)

Figure 1: Circuit symbols for (a) NMOS Transistor (b) PMOS Transistor

MOSFET Characterization

Figure 2 shows a characterization circuit for an NMOS transistor. To obtain ID as a function of VGS , V1 is swept while V2 is kept constant. If V1 is kept constant and V2 is swept, ID can be obtained as a function of VDS .

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Figure 2: NMOS✁✂✄☎transistor✝✠✁ characterization✁✞✟✂☎ circuit


c    Department of Electrical and Computer Engineering, Texas A&M University

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Characterization circuit for a PMOS transistor is shown in Fig. 3. Keeping V2 constant and sweeping V1 provides ID as a function of VSG . Sweeping V2 while V1 is kept constant provides the ID vs. VSD characteristics.



Figure 3:✁ PMOS✂✄☎✆transistor✡✁✞ characterization✁✟✠✝✞✄✂✆ circuit









Figure 4(a) shows the drain current (ID ) of an NMOS transistor as a function of VGS . Transistor parameters such as the threshold voltage (Vt ) and the transconductance parameter (k0 W =L or ) can be obtained by taking the derivative of ID with respect to VGS , as depicted in Fig. 4(b). In this plot, k0 W =L (or ) is the slope of the line, whereas Vt is the intersection with the VGS axis.


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✄ ✄✁ ✂ ☛☞✌✍☛✎✂✁(a)  ☎ ☎✁ ✆


✄✄✄✝✆


✓✔✕✖✗✘✙✚✛✜✢

☛✄✄☎




✡






✠✄✄✂


✑✒



✄✄✁✄











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✝ ☞✌✍✎☞✏(b)✝✞
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Figure 4: NMOS characterization (a) ID vs. VGS (b)
dID
vs. VGS




dVGS

Simulations

For all simulations, provide screenshots showing the schematics and the plots with the simulated values prop-erly labeled.

As the first step, install MOS transistor library (UsrComp S ECEN.usr) to your circuit simulator, details are provided in the simulator manual.


    1. Draw the schematics for the NMOS characterization circuit in Fig. 2 using the 2N7000G transistor.

        (a) Perform a DC sweep of V1 from 0V to 2.5V while V2 = 5V , and plot ID and its derivative as a function of
VGS .

        (b) Find the threshold voltage Vt and the transconductance parameter k0 WL (or  ).

    2. Repeat (1) for the CD4007N transistor.

    3. Draw the schematics for the PMOS characterization circuit in Fig. 3 using the CD4007P transistor.


(a) Perform a DC sweep of V1 from -2.5V to 0V while V2 = 5V , and plot ID and its derivative as a function of VSG .

(b) Find the threshold voltage Vt and the transconductance parameter k0 WL (or    ).





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Measurements

For all measurements, provide screenshots showing the plots with the measured values properly labeled.

    1. Build the NMOS characterization circuit in Fig. 2 using the 2N7000G transistor.

        (a) Apply a ramp signal from 0V to 2.5V at 1Hz for V1 while V2 = 5V . Export the voltage measurements from the scope to Excel, and plot ID as a function of VGS .

(b) Plot the derivative of ID as a function of VGS and find Vt and k0 WL as depicted in Fig. 4(b). In Ex-cel, dID =dVGS can be calculated as shown with the column ID’ in Fig. 5, starting with the formula (B3-B2)/(A3-A2). However, due to noise in the measured data, taking the derivative without filtering can result in the ID’ plot shown in Fig. 6(a). Using decimation provides filtering and reduces the noise in ID’. The column ID’ (decimated) in Fig. 5 shows the starting formula (to be copied to all cells below), and the resulting plot is shown in Fig. 6(b). In this plot, a decimation factor of 300 is used. The corresponding VGS should also be shifted as shown with the VGS (adjusted) column in Fig. 5.









Figure 5: Implementation of derivation and decimation in Excel




    2. Repeat (1) for the CD4007N transistor. See Fig. 7 for the internal schematics of CD4007 chip, connect pin 7 to GND and pin 14 to +5V supply voltage.

VDD


Figure 7: Schematic diagram of CD4007 chip


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    3. Build the PMOS characterization circuit in Fig. 3 using the CD4007P transistor, connect pin 7 to -5V supply voltage and pin 14 to GND.

(a) Apply a ramp signal from -2.5V to 0V at 1Hz for V1 while V2 = 5V . Export the voltage measurements from the scope to Excel, and plot ID as a function of VSG .

    (b) Plot the derivative of ID as a function of VSG , and find Vt and k0 WL as described in 1(b).


Report

    1. Include schematics, simulation plots, and measurement plots.

    2. Prepare a table showing simulated and measured results.

    3. Compare the results and comment on the differences.

Demonstration

    1. Build the characterization circuits in Figs. 2 and 3 for 2N7000G, CD4007N and CD4007P transistors on your breadboard and bring it to your lab session.

    2. Your name and UIN must be written on the side of your breadboard.

    3. Submit your report to your TA at the beginning of your lab session.

    4. Using the characterization circuits, obtain Vt and k0 WL for 2N7000G, CD4007N and CD4007P transistors as described.







































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