In this project, you will use Altera Quartus II with Verilog. You will design the 32-bit MIPS processor fully supporting all core instructions on green card at MIPS book or given below:
Any improvement over the schematic at the book can get extra points. Taking the instructions through UART communication from the PC is a bonus with 25 extra pts. We will supply UART verilog moodle for the bonus part. You can collect at most 150 points from this project. This project is worth 10% in total grading. Not executing projects can get at most 30pts.
Problem Session
In the problem session the details of the project will be explained in detail. It is a must to attend that session. We will take attendance at that PS and accept questions only from the ones attending the PS. The PS will be announced from Moodle.
Project Report
Reporting is important in this project. We want detailed reports for all Verilog files and your project. Your report will have Introduction, Method and Results parts:
Introduction: How you designed the processor. The big picture and the main ideas. The module diagram of the whole project and brief explanation of the aim of each module.
Method: Inputs and outputs of each module are explained and the detailed explanation of each module.
Results: Explanation of testbench and simulation results. Put results as images to this section.
Report is very important because the grading of your project will be done according to the synchronicity of your report with your design. Report can be wither Turkish or English but not a mix of both.
Demo
You will show your circuit executing properly during demo. You have at most 3 minutes to prove that. So be ready for the demo. It is ONLY your responsibility to show and explain the execution of your project. We will also ask you questions about your design. So, be ready for the demo, otherwise you can’t get good grades.
Comments
You must comment your Verilog code. At the start of each module the inputs and outputs and the purpose of the module will be explained. Also the different parts in the Verilog code must be commented.
Submit your project report pdf and the Altera Project folder as a zip file named YourName_YourSurname_YourId.zip to Moodle before due date.
No late submissions even if it is 1 minute. No medical reports. No excuses. No cry. So start early.
Any cheating attempt with the previous years’ projects or with your friends or Internet will result in at least -100 and at most -300. No matter you gave or take the code. Protect your code. Do it yourself for your own good.
