The following questions are based on the enhanced AVR datapath (see Figures 8.24 and 8.26 in the text). The microoperation for the Fetch cycle is shown below.
Stage Micro-operations
IF IR←M[PC],PC←PC+1,NPC←PC+1,RAR←PC+1
[25 pts]
1- Consider the implementation of the CLR Rd (Clear Register) instruction on the enhanced AVR datapath.
List and explain the sequence of microoperations required to implement CLR Rd. Note that this instruction takes a single execute cycle (EX).
List and explain the control signals and the Register Address Logic (RAL) output for the execute cycle of the CLR Rd instruction.
Control signals for the Fetch cycle are given below. Clearly explain your reasoning
Control
CLR
IF
RAL
CLR
Signals
EX
Output
EX
MJ
0
wA
MK
0
wB
ML
0
rA
IR_en
1
rB
PC_en
1
PCh_en
0
PCl_en
0
NPC_en
1
SP_en
0
DEMUX
x
MA
x
MB
x
ALU_f
xxxx
MC
xx
RF_wA
0
RF_wB
0
MD
x
ME
x
DM_r
x
DM_w
0
MF
x
MG
x
Adder_f
xx
Inc_Dec
x
MH
x
MI
x
[25 pts]
2- Consider the implementation of the STD Y+q, Rr (Store Indirect with Displacement) instruction on the enhanced AVR datapath.
List and explain the sequence of microoperations required to implement STD Y+q, Rr. Note that this instruction takes two execute cycles (EX1 and EX2).
List and explain the control signals and the Register Address Logic (RAL) output for the STD Y+q, Rr
instruction.
Control signals for the Fetch cycle are given below. Clearly explain your reasoning.
Control
IF
STD Y+q, Rr
Signals
EX1
EX2
MJ
0
MK
0
ML
0
IR_en
1
PC_en
1
PCh_en
0
PCl_en
0
NPC_en
1
SP_en
0
DEMUX
x
MA
x
MB
x
ALU_f
xxxx
MC
xx
RF_wA
0
RF_wB
0
MD
x
ME
x
DM_r
x
DM_w
0
MF
x
MG
xx
Adder_f
xx
Inc_Dec
x
MH
x
MI
x
[25 pts]
3- Consider the implementation of the ICALL (Indirect Call to Subroutine) instruction on the enhanced AVR datapath.
List and explain the sequence of microoperations required to implement ICALL. Note that this instruction takes two execute cycles (EX1 and EX2).
List and explain the control signals and the Register Address Logic (RAL) output for each execute cycle of the ICALL instruction
Control signals for the Fetch cycle are given below. Clearly explain your reasoning
Control
IF
ICALL
Signals
EX1
EX2
RAL
ICALL
Output
EX1
EX2
MJ
0
wA
MK
0
wB
ML
0
rA
IR_en
1
rB
PC_en
1
PCh_en
0
PCl_en
0
NPC_en
1
SP_en
0
DEMUX
x
MA
x
MB
x
ALU_f
xxxx
MC
xx
RF_wA
0
RF_wB
0
MD
x
ME
x
DM_r
x
DM_w
0
MF
x
MG
x
Adder_f
xx
Inc_Dec
x
MH
x
MI
x
[25 pts]
4- Consider the implementation of the LPM R7, Z (Load Program Memory) instruction on the enhanced AVR datapath.
List and explain the sequence of microoperations required to implement LPM R7, Z.
List and explain the control signals and the Register Address Logic (RAL) output for the LPM R7, Z instruction (complete all missing entries in the tables below).
Note that this instruction takes three execute cycles (EX1, EX2, and EX3).
Control signals for the Fetch cycle are given below. Clearly explain your reasoning.
Control
IF
LPM R7, Z
Signals
EX1
EX2
EX3
MJ
0
x
x
x
MK
0
x
x
x
ML
0
IR_en
1
PC_en
1
PCh_en
0
PCl_en
0
NPC_en
1
x
x
x
SP_en
0
DEMUX
x
MA
x
MB
x
ALU_f
xxxx
xxxx
xxxx
xxxx
MC
xx
RF_wA
0
RF_wB
0
MD
x
ME
x
DM_r
x
DM_w
0
MF
x
MG
x
Adder_f
xx
Inc_Dec
x
x
x
x
MH
x
x
x
x
MI
x
x
x
x
RAL
LPM R7, Z
Output
EX1
EX2
EX3
wA
wB
rA
rB
