CS223 Laboratory Project Single-cycle processor

The purpose of this project is to build a simplified single-cycle processor (Single-cycle processor: an instruction is fetched from memory, it is executed, and the results are stored all in a single clock cycle.) on Basys 3 board that would be capable of performing several types of instructions. The processor you will design will perform several functions depending on the 16-bit instructions on 8-bit data. Your design should include instruction memory, data memory, a register file and an arithmetic logic unit (ALU). The instruction memory should be a read-only memory. Data memory should be able to hold 16x8-bit data. Instructions to be executed should be either picked from the instruction memory, or from the switches on Basys3. Depending on the instruction, processor should do addition, load/store, and branch operations.




Instructions:




The processor will work on 16-bit instructions where the most significant 3-bits will be used as the opcode (abbreviated from operation code, also known as instruction code is the portion of a machine language instruction that specifies the operation to be performed.). Depending on the opcode, the controller will decide what to do, how to interpret the rest of the instruction, and send the necessary control signals back to datapath.




 Opcode
Function
000
Store Value
001
Load Value
010
Addition
011
Reserved
100
Reserved
 101
Branch if equals
110
Reserved
111
Reserved



Table 1: Instruction Set




Store Value:




If the opcode is 1’b000, the next bit will decide if the value to store should come immediately taken from instruction or from a register in the register file. If the value is 1, the next 4-bits will be used as the write address for data memory, and the remaining least significant 8 bits will be used as the data value to be written. For example, instruction 000_1_0101_00000011 can be translated as “write value 3 to address 5 of the data memory,” and therefore, address 5 of the data memory must be 5 after this instruction is executed.




                  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


Ex: 001_0_XXXX_0010_0011 will mean that write the value of address 3 in data memory into 2nd register in register file.




Addition:




The format for addition is as follows:




                 [15:13]
[12]


[11:8] Write
[7:4] Read
[3:0] Read
Opcode=010
Ignored (don’t


Register Address
Register Addr 1
Register Addr 2


care)












Table 5: Addition Instruction





Ex 1: Instruction: 010_X_0000_0000_0001 will add the values in Register 0 and Register 1 and put the result in Register 0, similar to “rf[0] += rf[1];” in a high level language.




Ex 2: Instruction: 010_X_0000_0001_0002 will add the values in Register 0 and Register 1 and put the result in Register 0, similar to “rf[0] = rf[1] + rf[2];” in a high level language.










Branch if equals:




The format for branch if equals is as follows:




 


Stop Execution (Wait)




   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Interface:




Push buttons, switches and seven-segment display will be used to interact with the processor. Seven-segment display will be used to show the address and the data in memory with a separator in middle (Figure 1). Right and left pushbuttons will be used to circulate in data memory. Assume initially seven-segment displays address 0 in the first digit and the correlated value in hex in the last 2 digits, pressing right button should display address 1 and the correlated value, whereas pressing left button should display address 0xF and the correlated data. The upper pushbutton will be used for reset. Middle pushbutton will be used to execute the instruction entered on switches whereas the down pushbutton will be used to execute the next instruction on instruction memory. The instruction to be executed next should be displayed in LEDs.

  















































Figure 1: Memory Display




Report:




Write a report that will contain the following:




Block diagram of your controller/datapath and explanation.



Detailed state diagram of the controller and explanation.



You are required to write SystemVerilog code for:



The implementation of the single-cycle processor instruction set given in Table 1.



Push button, switch and seven-segment display interfaces in order to interact with the processor.



For the following code, workout the code in single-cycle processor instruction set and show that it works in your processor (don’t care overflows and operate with only unsigned data):



[15] = [ [0]&0 0 ] ∗ [ [1]&0 0 ];