Computer Project #8 Solution

Assignment Overview

This assignment focuses on the interactions between registers, the data cache, and primary storage. You will design and implement additional functionality to extend the previous project, as described below.

It is worth 50 points (5% of course grade) and must be completed no later than 11:59 PM on Thursday, 3/25.

Assignment Deliverables

The deliverables for this assignment are the following files:

proj08.makefile – the makefile which produces proj08 proj08.student.cpp – the source code file for your solution

Be sure to use the specified file names and submit them for grading via the CSE Handin system before the project deadline.

Assignment Specifications

The system to be simulated is a 16-bit microprocessor: it has sixteen 16-bit general purpose registers and 16-bit physical addresses (and thus has 65,536 bytes of RAM). The data cache is a direct-mapped, write-back cache which contains eight lines. Each cache line contains control bits (valid bit, modified bit, and tag bits) and an 8-byte data block.

    1. The program will simulate the interactions between the register unit, the data cache, and primary storage by processing a file which contains zero or more instructions. Each line of the file will contain the following information:

        a) operation ("LDR" for "load into register" or "STR" for "store from register")
        b) register number (one hexadecimal digit)
        c) physical address (four hexadecimal digits, with leading zeroes)

Items in the line will be separated by exactly one space, and each line will terminate with a newline. For example:

LDR 5 ebd8

STR 4 0ac2
LDR a 0ad0

The first line represents an instruction where the two bytes at address ebd8 of RAM are loaded into register 5, and the second line represents an instruction where the two bytes in register 4 are stored into address 0ac2 of RAM.

    2. For each memory reference in the file, the program will display one line with the following information:

        a) operation ("LDR" or "STR")
        b) register number (one hexadecimal digit)
        c) physical address (four hexadecimal digits, with leading zeroes)
        d) tag bits (three hexadecimal digits, with leading zeroes)
        e) cache line accessed (one hexadecimal digit)
        f) byte offset (one hexadecimal digit)
        g) result of access (one character; ‘H’ for hit and ‘M’ for miss)

        h) data value (four hexadecimal digits, with leading zeroes)

If the operation is "LDR", the data value will be the 2-byte value which is being copied from the data cache to the indicated register. If the operation is "STR", the data value will be the 2-byte value which is being copied from the indicated register into the data cache.
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:

LDR e a73c 29c 7 4 H 3f29
STR 1 58d6 163 2 6 M 1020

Note: the two lines of example output (above) are not related to the input examples and are only intended to illustrate the format of the output.

3. After the simulation is completed, the program will display the contents of the registers, the data cache, and RAM.

    a) The contents of all sixteen registers will be displayed, where each 4-bit register number is displayed in hexadecimal and the 16-bit contents are displayed in hexadecimal (four hexadecimal digits, with leading zeroes). For example:

R0: 0000
R4: 6789
R8: 0000
Rc: 0000
R1: 1020
R5: abcd
R9: 0000
Rd: 0000
R2:
0000
R6:
0000
Ra:
0032
Re:
3f29
R3:
0055
R7:
0000
Rb:
0000
Rf:
0000

    b) The contents of the data cache will be displayed, with one line for each data cache entry:

        a) index of the data cache entry (one hexadecimal digit)
        b) V bit (one character; ‘0’ for not valid, ‘1’ for valid)

        c) M bit (one character; ‘0’ for not modified, ‘1’ for modified)
        d) tag bits (three hexadecimal digits, with leading zeroes)
        e) data block (eight bytes of data, where each byte is given as two hexadecimal digits, with leading zeroes)

The data cache display will include appropriate column headers. For example:

V M Tag    0    1    2    3    4    5    6    7
------------------------------------
[0]: 0 0 000 00 00 00 00 00 00 00 00
[1]: 0 0 000 00 00 00 00 00 00 00 00
[2]: 1 1 163 00 00 00 00 00 00 10 20

[3]: 0 0 000 00 00 00 00 00 00 00 00
[4]: 1 0 03a 00 11 22 33 44 55 66 77
[5]: 0 0 000 00 00 00 00 00 00 00 00
[6]: 0 0 000 00 00 00 00 00 00 00 00
[7]: 1 0 29c 00 00 00 00 3f 29 00 00

    c) The contents of the first 128 bytes of RAM will be displayed. Each line of that display will include an address (four hexadecimal digits, with leading zeroes) and the sixteen bytes of data starting at that address (two hexadecimal digits, with leading zeroes). For example:

0000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0020: ba 76 21 84 00 00 00 00 00 00 00 00 00 00 00 00
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0050: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff 00 00
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Note: the example displays (above) are only intended to illustrate the format of the output.

    4. Command line arguments will be used to specify the name of the file which contains the instructions to be processed (the "-input" option), the name of the file which contains the initial contents of RAM (the "-ram" option), and to display debugging information (the "-debug" option).
    a) The "-input" option will be followed by the name of the file which contains zero or more instructions (as defined above).

    b) If selected, the "-ram" option will be followed by the name of the file which contains the initial contents of a subset of RAM. Each line of that file will contain an address which is a multiple of 16 (four hexadecimal digits, with leading zeroes), followed by sixteen bytes of data (two hexadecimal digits, with leading zeroes). For example:

0040 10 45 1b 00 ff 00 00 00 00 00 00 00 00 00 00 00 0070 00 00 a7 00 00 9c 00 00 00 00 00 00 00 00 00 00 ffc0 00 11 22 33 00 00 00 00 00 00 00 00 cc dd ee ff

5. If selected, the "-debug" option will cause the program to display debugging information.

    a) After all program initialization has occurred and immediately before the first line of the "-input" file is processed, the program will display the contents of the registers, the data cache, and RAM (using the same format as #3 above).

    b) The contents of the data cache after each instruction is processed.

6. The program will include appropriate logic to handle exceptional cases and errors.

Assignment Notes

    1. As stated above, your source code file will be named "proj08.student.cpp" and you must use "g++" to translate your source code file in the CSE Linux environment.
.
    2. Valid executions of the program might appear as follows:

proj08 –input testA

proj08 –debug –input testB

proj08 –ram initialRAM –input testC proj08 –ram initialRAM –input testD -debug

3. Your program may assume that the "-input" and the "-ram" files are formatted correctly:

    a) If the "-input" file can be accessed, the contents will be valid as per #1 under "Assignment Specifications".

    b) If the "-ram" file can be accessed, the contents will be valid as per #4 under "Assignment Specifications".

4. Your program must create the following data structures:

    a) A data structure representing the registers. All sixteen registers will be initialized to zero at the start of the simulation.

    b) A data structure representing the data cache. All of the entries will be initialized to zero at the start of the simulation.

    c) A data structure representing the RAM. All of the entries will be initialized to zero at the start of the simulation. If the user selects the "-ram" option, a subset of the RAM will be re-initialized using the contents of the specified file.

    5. Assume that the microprocessor uses a "big endian" memory model: the most significant byte of a 2-byte item is stored in the lowest numbered memory address, and the least significant byte is stored at the highest numbered memory address.

For example, if the value 0xabcd is copied into memory at address 0x0214, then the byte at address 0x0214 in RAM will contain the value 0xab and the byte at address 0x0215 in RAM will contain the value 0xcd.

    6. Assume that the microprocessor uses an aligned memory model: the address of a 2-byte item will always be a multiple of 2 (and thus the least significant bit will be 0).