21
You have to implement instruction and data memory and register modules. Use your 1-bit ALU in your previous design as a module.
You have to write your own testbench on Verilog and show that the project is working right.
Learn how to initialize and read a memory in PS.
Write a report that explains your Verilog modules and the testbench results. You should test all operations that ALU allows. Also report how many logic gates you used for the ALU.
RULES!!!
Other than register and memory, you cannot use any other logic gates than AND, OR and NOT. (For instance XOR is not allowed.)
You can only use structural Verilog. No dataflow, no assign statement no behavioral Verilog.
ONLY THE INSTRUCTIONS IN THE TABLE WILL BE SUPPORTED. OTHERWISE 0pts.
Any not simulating Verilog project gets at most 20pts.
Any cheating means -100pts whether giving or taking the design.
You have to use hierarchy and different modules as described here.
The project will be explained in PS. So attend the PS.
If you can show your design working on actual FPGA board than you get 20pts.
