Objective
Review synchronous sequential circuits.
Review counter logics.
Prerequisite
Fundamentals of logic gates.
Clocking concepts
Logic modeling in Verilog HDL.
Pre-labs
Consider a 4-bit synchronous binary up counter.
1.1 Draw the logic diagram
1.2 Construct Verilog RTL representation for the logics with verification.
Experiments
1 Frequency Divider: Construct a 27-bit synchronous binary counter. Use the MSB of the counter, we can get a frequency divider which provides a 1/227 frequency output (fout) of the original clock (fcrystal, 100MHz). Construct a frequency divider of this kind.
1.1
Write the specification of the frequency divider.
1.2
Draw the block diagram of the frequency divider.
1.3
Implement the frequency divider with the following parameters.
I/O
fcrystal
fout
Site
W5
U16
2
Frequency Divider: Use a count-for-50M counter and some glue logics to construct a 1 Hz
clock frequency. Construct a frequency divider of this kind.
2.1
Write the specification of the frequency divider.
2.2
Draw the block diagram of the frequency divider.
2.3
Implement the frequency divider with the following parameters.
I/O
fcrystal
fout
Site
W5
U16
3
Construct a 4-bit synchronous binary up counter (b3b2b1b0) with the 1-Hz clock frequency
from exp2 and use 4 LEDs for display.
I/O
fcrystal
b3
b2
b1
b0
Site
W5
V19
U19
E19
U16
4
Construct a single digit BCD up counter with the divided clock as the clock frequency and
display on the seven-segment display.
© Ma, Hsi-Pin, Lab for Reliable Computing (LaRC), EE, NTHU. Spring, 2018
EE2230 Logic Design Lab
2
4.1 Construct a BCD up counter.
4.2 Construct a BCD-to-seven-segment display decoder.
4.3 Combine the above two together.
5 (Bonus) Construct a 30 seconds count down timer (stop at 00).
TA:
© Ma, Hsi-Pin, Lab for Reliable Computing (LaRC), EE, NTHU. Spring, 2018
